SPRSP93 November   2024 F29H850TU , F29H859TU-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  F29H85x ESD Ratings – Commercial
    3. 6.3  F29H85x ESD Ratings – Automotive
    4. 6.4  F29P58x ESD Ratings – Commercial
    5. 6.5  F29P58x ESD Ratings – Automotive
    6. 6.6  Recommended Operating Conditions
    7. 6.7  Power Consumption Summary
      1. 6.7.1 System Current Consumption VREG Enabled
      2. 6.7.2 System Current Consumption VREG Disable - External Supply
      3. 6.7.3 Operating Mode Test Description
      4. 6.7.4 Reducing Current Consumption
        1. 6.7.4.1 Typical Current Reduction per Disabled Peripheral
    8. 6.8  Electrical Characteristics
    9. 6.9  Thermal Resistance Characteristics for ZEX Package
    10. 6.10 Thermal Resistance Characteristics for PTS Package
    11. 6.11 Thermal Resistance Characteristics for RFS Package
    12. 6.12 Thermal Resistance Characteristics for PZS Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset XRSn Timing Requirements
          2. 6.14.2.2.2 Reset XRSn Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
        3. 6.14.3.3 Input Clocks
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.14.3.4.7.3 Crystal Oscillator Parameters
            4. 6.14.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  Memory Subsystem (MEMSS)
        1. 6.14.5.1 Introduction
        2. 6.14.5.2 Features
        3. 6.14.5.3 RAM Specifications
      6. 6.14.6  Debug/JTAG
        1. 6.14.6.1 JTAG Electrical Data and Timing
          1. 6.14.6.1.1 DEBUGSS Timing Requirements
          2. 6.14.6.1.2 DEBUGSS Switching Characteristics
          3. 6.14.6.1.3 JTAG Timing Diagram
          4. 6.14.6.1.4 SWD Timing Diagram
      7. 6.14.7  GPIO Electrical Data and Timing
        1. 6.14.7.1 GPIO – Output Timing
          1. 6.14.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.7.1.2 General-Purpose Output Timing Diagram
        2. 6.14.7.2 GPIO – Input Timing
          1. 6.14.7.2.1 General-Purpose Input Timing Requirements
          2. 6.14.7.2.2 Sampling Mode
        3. 6.14.7.3 Sampling Window Width for Input Signals
      8. 6.14.8  Real-Time Direct Memory Access (RTDMA)
        1. 6.14.8.1 Introduction
          1. 6.14.8.1.1 Features
          2. 6.14.8.1.2 Block Diagram
      9. 6.14.9  Low-Power Modes
        1. 6.14.9.1 Clock-Gating Low-Power Modes
        2. 6.14.9.2 Low-Power Mode Wake-up Timing
          1. 6.14.9.2.1 IDLE Mode Timing Requirements
          2. 6.14.9.2.2 IDLE Mode Switching Characteristics
          3. 6.14.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.9.2.4 STANDBY Mode Timing Requirements
          5. 6.14.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.9.2.6 STANDBY Entry and Exit Timing Diagram
      10. 6.14.10 External Memory Interface (EMIF)
        1. 6.14.10.1 Asynchronous Memory Support
        2. 6.14.10.2 Synchronous DRAM Support
        3. 6.14.10.3 EMIF Electrical Data and Timing
          1. 6.14.10.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.14.10.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.14.10.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.14.10.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.14.10.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.14.10.3.6 EMIF Asynchronous Memory Timing Diagrams
    15. 6.15 C29x Analog Peripherals
      1. 6.15.1 Analog Subsystem
        1. 6.15.1.1 Features
        2. 6.15.1.2 Block Diagram
        3. 6.15.1.3 Analog Pin Connections
      2. 6.15.2 Analog-to-Digital Converter (ADC)
        1. 6.15.2.1 ADC Configurability
          1. 6.15.2.1.1 Signal Mode
        2. 6.15.2.2 ADC Electrical Data and Timing
          1. 6.15.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.15.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.15.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.15.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.15.2.2.5  ADC Timing Requirements
          6. 6.15.2.2.6  ADC Characteristics 12-bit Single-Ended
          7. 6.15.2.2.7  ADC Characteristics 12-bit Differential
          8. 6.15.2.2.8  ADC Characteristics 16-bit Single-Ended
          9. 6.15.2.2.9  ADC Characteristics 16-bit Differential
          10. 6.15.2.2.10 ADC INL and DNL
          11. 6.15.2.2.11 ADC Input Model Models
          12. 6.15.2.2.12 ADC Timing Diagrams
      3. 6.15.3 Temperature Sensor
        1. 6.15.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.3.1.1 Temperature Sensor Characteristics
      4. 6.15.4 Comparator Subsystem (CMPSS)
        1. 6.15.4.1 CMPSS Connectivity Diagram
        2. 6.15.4.2 Block Diagram
        3. 6.15.4.3 CMPSS Electrical Data and Timing
          1. 6.15.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.4.3.3 CMPSS Illustrative Graphs
      5. 6.15.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.5.1 Buffered DAC Electrical Data and Timing
          1. 6.15.5.1.1 Buffered DAC Operating Conditions
          2. 6.15.5.1.2 Buffered DAC Electrical Characteristics
    16. 6.16 C29x Control Peripherals
      1. 6.16.1 Enhanced Capture (eCAP)
        1. 6.16.1.1 eCAP Block Diagram
        2. 6.16.1.2 eCAP Synchronization
        3. 6.16.1.3 eCAP Electrical Data and Timing
          1. 6.16.1.3.1 eCAP Timing Requirements
          2. 6.16.1.3.2 eCAP Switching Characteristics
      2. 6.16.2 High-Resolution Capture (HRCAP)
        1. 6.16.2.1 eCAP and HRCAP Block Diagram
        2. 6.16.2.2 HRCAP Electrical Data and Timing
          1. 6.16.2.2.1 HRCAP Switching Characteristics
          2. 6.16.2.2.2 HRCAP Figure and Graph
      3. 6.16.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.3.1 Control Peripherals Synchronization
        2. 6.16.3.2 ePWM Electrical Data and Timing
          1. 6.16.3.2.1 ePWM Timing Requirements
          2. 6.16.3.2.2 ePWM Switching Characteristics
          3. 6.16.3.2.3 Trip-Zone Input Timing
            1. 6.16.3.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      4. 6.16.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.16.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.5.1 HRPWM Electrical Data and Timing
          1. 6.16.5.1.1 High-Resolution PWM Characteristics
      6. 6.16.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.6.1 eQEP Electrical Data and Timing
          1. 6.16.6.1.1 eQEP Timing Requirements
          2. 6.16.6.1.2 eCAP Switching Characteristics
      7. 6.16.7 Sigma-Delta Filter Module (SDFM)
        1. 6.16.7.1 SDFM Electrical Data and Timing
          1. 6.16.7.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
          2. 6.16.7.1.2 SDFM Electrical Data and Timing (Using ASYNC)
            1. 6.16.7.1.2.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
            2. 6.16.7.1.2.2 SDFM Timing Requirements When Using Synchronous GPIO SYNC Option
          3. 6.16.7.1.3 SDFM Timing Diagram
    17. 6.17 C29x Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Fast Serial Interface (FSI)
        1. 6.17.2.1 FSI Transmitter
          1. 6.17.2.1.1 FSITX Electrical Data and Timing
            1. 6.17.2.1.1.1 FSITX Switching Characteristics
            2. 6.17.2.1.1.2 FSITX Timings
        2. 6.17.2.2 FSI Receiver
          1. 6.17.2.2.1 FSIRX Electrical Data and Timing
            1. 6.17.2.2.1.1 FSIRX Timing Requirements
            2. 6.17.2.2.1.2 FSIRX Switching Characteristics
            3. 6.17.2.2.1.3 FSIRX Timings
        3. 6.17.2.3 FSI SPI Compatibility Mode
          1. 6.17.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 6.17.3 Inter-Integrated Circuit (I2C)
        1. 6.17.3.1 I2C Electrical Data and Timing
          1. 6.17.3.1.1 I2C Timing Requirements
          2. 6.17.3.1.2 I2C Switching Characteristics
          3. 6.17.3.1.3 I2C Timing Diagram
      4. 6.17.4 Power Management Bus (PMBus) Interface
        1. 6.17.4.1 PMBus Electrical Data and Timing
          1. 6.17.4.1.1 PMBus Electrical Characteristics
          2. 6.17.4.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.4.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.4.1.4 PMBus Standard Mode Switching Characteristics
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.17.5.1.3 SPI Controller Mode Timing Requirements
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.17.5.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Single Edge Nibble Transmission (SENT)
        1. 6.17.6.1 Introduction
        2. 6.17.6.2 Features
      7. 6.17.7 Local Interconnect Network (LIN)
      8. 6.17.8 EtherCAT SubordinateDevice Controller (ESC)
        1. 6.17.8.1 ESC Features
        2. 6.17.8.2 ESC Subsystem Integrated Features
        3. 6.17.8.3 EtherCAT IP Block Diagram
        4. 6.17.8.4 EtherCAT Electrical Data and Timing
          1. 6.17.8.4.1 EtherCAT Timing Requirements
          2. 6.17.8.4.2 EtherCAT Switching Characteristics
          3. 6.17.8.4.3 EtherCAT Timing Diagrams
      9. 6.17.9 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Error Signaling Module (ESM_C29)
      1. 7.3.1 Introduction
      2. 7.3.2 ESM Subsystem
      3. 7.3.3 System ESM
    4. 7.4  Error Aggregator
      1. 7.4.1 Error Aggregator Modules
      2. 7.4.2 Error Aggregator Interface
    5. 7.5  Memory
      1. 7.5.1 C29x Memory Map
      2. 7.5.2 Flash Memory Map
        1. 7.5.2.1 Flash MAIN Region Address Map (F29H85x, 4MB)
        2. 7.5.2.2 Flash MAIN Region Address Map (F29H85x, 2MB)
        3. 7.5.2.3 Flash MAIN Region Address Map (F29P58x, 4MB)
        4. 7.5.2.4 Flash MAIN Region Address Map (F29P58x, 2MB)
        5. 7.5.2.5 Flash MAIN Region Address MAP (F29P58x, 1MB)
        6. 7.5.2.6 Flash Data Bank Address Map
        7. 7.5.2.7 Flash BANKMGMT Region Address Map
        8. 7.5.2.8 Flash SECCFG Region Address Map
      3. 7.5.3 Peripheral Registers Memory Map
    6. 7.6  Identification
    7. 7.7  Boot ROM
      1. 7.7.1 Device Boot Sequence
      2. 7.7.2 Device Boot Modes
        1. 7.7.2.1 Default Boot Modes
        2. 7.7.2.2 Custom Boot Modes
      3. 7.7.3 Device Boot Configurations
        1. 7.7.3.1 Configuring Boot Mode Pins
        2. 7.7.3.2 Configuring Boot Mode Table Options
      4. 7.7.4 Device Boot Flow Diagrams
        1. 7.7.4.1 Device Boot Flow
        2. 7.7.4.2 CPU1 Boot Flow
        3. 7.7.4.3 Emulation Boot Flow
        4. 7.7.4.4 Stand-alone Boot Flow
      5. 7.7.5 GPIO Assignments
    8. 7.8  Security Modules and Cryptographic Accelerators
      1. 7.8.1 Security Modules
        1. 7.8.1.1 Hardware Security Module (HSM)
        2. 7.8.1.2 Cryptographic Accelerators
      2. 7.8.2 Safety and Security Unit (SSU)
        1. 7.8.2.1 System View
    9. 7.9  C29x Subsystem
      1. 7.9.1 C29 CPU Architecture
      2. 7.9.2 Peripheral Interrupt Priority and Expansion (PIPE)
        1. 7.9.2.1 Introduction
          1. 7.9.2.1.1 Features
          2. 7.9.2.1.2 Interrupt Concepts
        2. 7.9.2.2 Interrupt Architecture
          1. 7.9.2.2.1 Dynamic Priority Arbitration Block
          2. 7.9.2.2.2 Post Processing Block
          3. 7.9.2.2.3 Memory Mapped Registers
        3. 7.9.2.3 Interrupt Propagation
      3. 7.9.3 Data Logging and Trace (DLT)
        1. 7.9.3.1 Introduction
          1. 7.9.3.1.1 Features
            1. 7.9.3.1.1.1 Block Diagram
      4. 7.9.4 Waveform Analyzer Diagnostics (WADI)
        1. 7.9.4.1 WADI Overview
          1. 7.9.4.1.1 Features
          2. 7.9.4.1.2 Block Diagram
          3. 7.9.4.1.3 Description
      5. 7.9.5 Embedded Real-Time Analysis and Diagnostic (ERAD)
      6. 7.9.6 Inter-Processor Communications (IPC)
        1. 7.9.6.1 Introduction
      7. 7.9.7 Watchdog
      8. 7.9.8 Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9 Configurable Logic Block (CLB)
    10. 7.10 Lockstep Compare Module (LCM)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
    2.     TRAY

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PTS|176
  • RFS|144
  • ZEX|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5.1 GPIO Muxed Pins

Table 5-7 GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
GPIO0 EPWM1_A EMIF1_A13 EMIF1_D0 MCAND_TX I2CA_SDA UARTE_TX OUTPUTXBAR9 ESC_TX0_DATA0 ESC_GPI0 FSITXA_D0
GPIO1 EPWM1_B EMIF1_A14 EMIF1_D3 MCAND_RX I2CA_SCL UARTE_RX OUTPUTXBAR10 ESC_TX1_DATA0 ESC_GPI1 FSITXA_D1
GPIO2 EPWM2_A EMIF1_A15 EMIF1_D4 UARTA_TX I2CB_SDA MCANF_TX OUTPUTXBAR1 ESC_RX1_ERR ESC_GPI2 FSITXA_CLK
GPIO3 EPWM2_B EMIF1_A16 EMIF1_D5 UARTA_RX I2CB_SCL MCANF_RX OUTPUTXBAR2 ESC_GPI3 FSIRXA_D0
GPIO4 EPWM3_A EMIF1_A17 EMIF1_D9 MCANC_TX UARTF_TX OUTPUTXBAR3 ESC_GPI4 FSIRXA_D1 ERRORSTS
GPIO5 EPWM3_B EMIF1_A18 EMIF1_D10 MCANC_RX UARTF_RX OUTPUTXBAR11 OUTPUTXBAR3 ESC_GPI5 FSIRXA_CLK
GPIO6 EPWM4_A EMIF1_DQM0 EMIF1_CLK MCANB_TX LINA_TX OUTPUTXBAR4 SYNCOUT ESC_GPI6 FSITXB_D0
GPIO7 EPWM4_B EMIF1_DQM1 EMIF1_CAS MCANB_RX LINA_RX OUTPUTXBAR5 ESC_GPI7 FSITXB_D1
GPIO8 EPWM5_A EMIF1_RAS EPWM4_B MCANC_TX SPIE_PICO UARTD_TX OUTPUTXBAR12 ADCSOCAO ESC_GPO0 FSITXB_CLK FSITXA_D1 FSIRXA_D0
GPIO9 EPWM5_B EMIF1_D11 SPIE_POCI UARTD_RX OUTPUTXBAR6 ESC_TX0_CLK ESC_GPO1 FSIRXB_D0 FSITXA_D0 FSIRXA_CLK
GPIO10 EPWM8_A PMBUSA_SCL ADCSOCBO MCANC_RX UARTC_TX I2CA_SCL SENT2 ESC_GPI19 ADCA_EXTMUXSEL2 OUTPUTXBAR13
GPIO11 EPWM6_B EMIF1_D15 EPWM7_B SPIE_PTE SD4_D1 PMBUSA_ALERT ESC_TX0_DATA1 ESC_GPO3 FSIRXB_CLK FSIRXA_D1 OUTPUTXBAR7
GPIO12 EPWM7_A EMIF1_A1 ADCSOCAO SPIE_CLK SD4_C2 PMBUSA_CTL ESC_TX0_DATA2 ESC_GPO4 FSIRXC_D0 FSIRXA_D0 OUTPUTXBAR14
GPIO13 EPWM7_B EMIF1_CS0n EMIF1_D9 UARTC_RX SD4_D2 PMBUSA_SDA ESC_TX0_DATA3 ESC_GPO5 FSIRXC_D1 FSIRXA_CLK OUTPUTXBAR15
GPIO14 EPWM6_A EMIF1_D17 EPWM18_A EMIF1_D13 LINA_TX OUTPUTXBAR3 PMBUSA_SCL ESC_PHY1_LINKSTATUS ESC_GPO6 FSIRXC_CLK SD4_C1 OUTPUTXBAR8
GPIO15 EPWM8_B PMBUSA_CTL I2CA_SDA LINA_RX OUTPUTXBAR4 SENT1 ESC_GPO7 ESC_GPI20 ADCA_EXTMUXSEL3 OUTPUTXBAR16
GPIO16 EPWM9_A EMIF1_D29 EMIF1_BA0 SPIA_PICO MCAND_TX ESC_RX1_CLK SD1_D1 FSIRXD_D1 FSIRXC_CLK OUTPUTXBAR7
GPIO17 EPWM9_B EMIF1_DQM3 EMIF1_BA1 SPIA_POCI MCAND_RX ESC_RX1_DV SD1_C1 FSIRXD_CLK UARTC_TX OUTPUTXBAR8
GPIO18 EPWM15_A PMBUSA_ALERT I2CA_SCL UARTC_RX SENT4 ESC_GPI21 ADCB_EXTMUXSEL0
GPIO19 EPWM10_B EMIF1_CS3n ADCSOCBO SPIA_PTE UARTE_RX MCANC_TX PMBUSA_ALERT ESC_TX1_DATA3 SD1_C2
GPIO20 EPWM11_A EMIF1_BA0 EMIF1_DQM2 SPIC_PICO MCANB_RX ESC_TX1_DATA2 SD1_D3
GPIO21 EPWM11_B EMIF1_BA1 SPIC_POCI MCANB_TX ESC_TX1_DATA1 SD1_C3
GPIO22 EPWM12_A PMBUSA_SDA I2CB_SDA UARTB_TX MCANC_TX SENT5 ESC_GPO2 ESC_GPI22 ADCB_EXTMUXSEL1
GPIO23 EPWM12_B PMBUSA_SCL I2CB_SCL UARTB_RX MCANC_RX SENT6 ESC_PHY_RESETn ESC_GPI23 ADCC_EXTMUXSEL0
GPIO24 EPWM13_A EMIF1_DQM0 SPIB_PICO LINB_TX MCANE_TX ESC_RX0_CLK SD2_D1 ESC_GPI24 EPWM2_A OUTPUTXBAR1
GPIO25 EPWM13_B EMIF1_DQM1 SPIB_POCI LINB_RX MCANE_RX PMBUSA_SDA ESC_RX0_DV SD2_C1 FSITXA_D1 EPWM2_B OUTPUTXBAR2
GPIO26 EPWM14_A EMIF1_DQM2 SPIB_CLK UARTE_TX MCANE_TX PMBUSA_CTL ESC_RX0_ERR SD2_D2 FSITXA_D0 ESC_MDIO_CLK OUTPUTXBAR3
GPIO27 EPWM14_B EMIF1_DQM3 SPIB_PTE UARTA_TX EPWM4_A ESC_RX0_DATA0 SD2_C2 FSITXA_CLK ESC_MDIO_DATA OUTPUTXBAR4
GPIO28 EPWM15_A EMIF1_CS4n EMIF1_CS2n UARTA_RX EPWM4_B ESC_RX0_DATA1 SD2_D3 OUTPUTXBAR5
GPIO29 EPWM15_B PMBUSA_SDA UARTE_RX I2CA_SDA SENT3 ESC_LATCH0 ESC_I2C_SDA ADCC_EXTMUXSEL1 OUTPUTXBAR6
GPIO30 EPWM16_A EMIF1_CLK EMIF1_CS4n MCANC_RX SPID_PICO EMIF1_A12 ESC_LATCH1 SD2_D4 ESC_I2C_SCL ESC_SYNC1 OUTPUTXBAR7
GPIO31 EPWM16_B EMIF1_WEn EMIF1_RNW MCANC_TX SPID_POCI I2CA_SDA ESC_RX1_DATA0 SD2_C4 FSITXD_D0 OUTPUTXBAR8
GPIO32 EMIF1_CS0n EMIF1_OEn SPIA_PICO SPID_CLK I2CA_SDA OUTPUTXBAR9 ESC_RX0_DATA0
GPIO33 EMIF1_RNW EMIF1_BA0 SPIA_POCI SPID_PTE I2CA_SCL OUTPUTXBAR10 ESC_LED_ERR
GPIO34 EPWM18_A EMIF1_CS2n EMIF1_BA1 SPIA_CLK UARTF_TX I2CB_SDA OUTPUTXBAR11 ESC_LATCH0 EPWM3_B ESC_SYNC0 OUTPUTXBAR1
GPIO35 EPWM18_B EMIF1_CS3n EMIF1_A0 SPIA_PTE UARTF_RX I2CB_SCL OUTPUTXBAR12 ESC_LATCH1 ESC_SYNC1
GPIO36 EMIF1_WAIT EMIF1_A1 UARTC_TX MCANC_RX OUTPUTXBAR13 SD1_D1 EMIF1_WEn
GPIO37 EPWM18_A EMIF1_OEn EMIF1_A2 UARTC_RX MCANC_TX OUTPUTXBAR14 ESC_RX1_DATA1 SD1_D2 EMIF1_D24 OUTPUTXBAR2
GPIO38 EPWM18_B EMIF1_A0 EMIF1_A3 UARTA_TX SPIE_PICO OUTPUTXBAR15 ESC_RX0_DATA1 SD1_D3 FSITXD_D1 EMIF1_CS2n
GPIO39 EMIF1_A1 EMIF1_A4 UARTA_RX OUTPUTXBAR16 ESC_MDIO_DATA SD1_D4 FSIRXD_CLK ESC_LED_RUN
GPIO40 EPWM13_A EMIF1_A2 MCANB_RX I2CB_SDA OUTPUTXBAR9 ESC_GPO2 SD4_C3 EPWM1_A SD2_C1
GPIO41 EPWM13_B EMIF1_A3 EPWM18_A MCANB_TX SPIE_POCI I2CB_SCL OUTPUTXBAR10 ESC_RX0_DATA2 SD4_D3 FSIRXD_CLK EPWM1_B SD2_D1
GPIO42 EPWM14_A EMIF1_A2 EMIF1_A13 UARTA_TX SPIE_CLK I2CA_SDA OUTPUTXBAR13 SD4_C3 SD4_C4 FSIRXD_D0 ADCE_EXTMUXSEL2
GPIO43 EPWM14_B EMIF1_A4 EMIF1_D13 UARTA_RX SPIE_PTE I2CA_SCL OUTPUTXBAR14 SD4_D4 FSIRXD_D1 ADCE_EXTMUXSEL3
GPIO44 EMIF1_A4 SPID_POCI MCANB_RX UARTB_TX OUTPUTXBAR14 ESC_TX1_CLK SD3_C4 FSIRXD_CLK
GPIO45 EMIF1_A5 SPID_PTE MCANB_TX UARTB_RX OUTPUTXBAR15 ESC_TX1_ENA SD3_D4 FSIRXD_D0
GPIO46 EPWM4_A EMIF1_A6 EPWM14_A UARTC_TX MCANE_TX ESC_MDIO_CLK SD3_C4
GPIO47 EPWM4_B EMIF1_A7 EPWM14_B UARTC_RX MCANE_RX ESC_MDIO_DATA SD4_C3
GPIO48 EMIF1_A8 UARTD_TX OUTPUTXBAR3 ESC_PHY_CLK SD1_D1 EPWM3_A SD2_C2
GPIO49 EMIF1_A9 EMIF1_A5 UARTD_RX OUTPUTXBAR4 ESC_TX1_DATA2 SD1_C1 FSITXA_D0 SD2_D1
GPIO50 EPWM15_A EMIF1_A10 EMIF1_A6 SPIC_PICO MCANF_TX ESC_TX1_DATA1 SD1_D2 FSITXA_D1 ESC_GPI25 SD2_D2
GPIO51 EPWM15_B EMIF1_A11 EMIF1_A7 SPIC_POCI MCANF_RX ESC_TX1_CLK SD1_C2 FSITXA_CLK ESC_GPI26 SD2_D3
GPIO52 EPWM16_A EMIF1_A12 EMIF1_A8 UARTD_TX SPIC_CLK ESC_TX1_ENA SD1_D3 FSIRXA_D0 SD2_D4
GPIO53 EPWM16_B EMIF1_D31 EMIF1_A9 UARTD_RX SPIC_PTE ESC_PHY0_LINKSTATUS SD1_C3 FSIRXA_D1 ESC_GPI28 SD1_C1
GPIO54 EMIF1_D30 EMIF1_A10 SPIA_PICO ESC_PHY_CLK SD1_D4 FSIRXA_CLK ESC_GPI29 SD1_C2
GPIO55 EPWM16_B EMIF1_D29 EMIF1_D0 SPIA_POCI EMIF1_WAIT ESC_PHY0_LINKSTATUS SD1_C4 FSITXB_D0 SD1_C3
GPIO56 EPWM17_A EMIF1_D28 EMIF1_D1 SPIA_CLK MCAND_TX I2CA_SDA ESC_PDI_UC_IRQ SD2_D1 FSITXB_CLK ESC_GPI30 SD1_C4
GPIO57 EPWM17_B EMIF1_D27 EMIF1_D2 SPIA_PTE MCAND_RX I2CA_SCL ESC_MDIO_DATA SD2_C1 FSITXB_D1 ESC_GPI31 SD3_D3
GPIO58 EPWM13_A EMIF1_D26 EPWM8_A SPIA_PICO MCANC_RX SENT1 ESC_LED_LINK0_ACTIVE SD2_D2 FSIRXB_D0 ESC_TX0_DATA3 SD2_C2
GPIO59 EPWM5_A EMIF1_D25 EPWM8_B SPIA_POCI MCANC_TX SENT2 ESC_LED_LINK1_ACTIVE SD2_C2 FSIRXB_D1 ESC_TX0_ENA SD2_C3
GPIO60 EPWM3_B EMIF1_D24 EMIF1_D0 SPIA_CLK OUTPUTXBAR3 SENT3 ESC_LED_ERR ESC_LATCH0 FSIRXB_CLK SD2_C4
GPIO61 EPWM17_B EMIF1_D23 EMIF1_D6 SPIA_PTE MCANC_RX OUTPUTXBAR4 ESC_LED_RUN SD2_C3 FSITXD_CLK ESC_LATCH1
GPIO62 EPWM17_A EMIF1_D22 EMIF1_D7 MCANC_RX MCANC_TX SENT4 ESC_LED_STATE_RUN SD2_D4 FSITXD_D0 ESC_MDIO_CLK
GPIO63 EPWM9_A EMIF1_D21 EMIF1_RNW SPIB_PICO MCANC_TX SENT5 ESC_RX1_DATA0 SD1_D1 FSITXD_D1 ADCD_EXTMUXSEL0 SD2_C4
GPIO64 EPWM9_B EMIF1_D20 EMIF1_WAIT SPIB_POCI MCANA_TX UARTF_TX SENT6 ESC_RX1_DATA1 SD1_C1 FSITXD_CLK ADCD_EXTMUXSEL1
GPIO65 EPWM10_A EMIF1_D19 EMIF1_WEn SPIB_CLK MCANA_RX UARTF_RX ESC_RX1_DATA2 SD1_D2 FSITXB_CLK ADCD_EXTMUXSEL2 ESC_GPI13
GPIO66 EPWM10_B EMIF1_D18 EMIF1_OEn SPIB_PTE I2CB_SDA ESC_RX1_DATA3 SD1_C2 FSITXB_D1 ADCD_EXTMUXSEL3 ESC_GPI14
GPIO67 EPWM17_A EMIF1_D17 LINB_TX MCAND_TX SD1_D3 FSITXB_CLK
GPIO68 EPWM17_B EMIF1_D16 EMIF1_D4 LINB_RX MCAND_RX EMIF1_D13 ESC_PHY1_LINKSTATUS SD1_C3 FSIRXB_D1 ESC_GPI15
GPIO69 EPWM11_A EMIF1_D15 SPIC_PICO I2CB_SCL ESC_RX1_CLK SD1_D4 FSITXB_D0
GPIO70 EPWM11_B EMIF1_D14 SPIC_POCI MCANC_RX UARTB_TX ESC_RX1_DV SD1_C4 FSIRXB_D0 ESC_GPI16
GPIO71 EPWM12_A EPWM11_A EMIF1_D5 SPIC_CLK MCANC_TX UARTB_RX EMIF1_D13 ESC_RX1_ERR SD3_D1 FSITXC_CLK FSITXB_D0
GPIO72 EPWM12_B EMIF1_D12 SPIC_PTE MCANB_RX UARTA_TX OUTPUTXBAR8 ESC_TX1_DATA3 SD3_D2 FSITXC_D0 SD3_C1
GPIO73 EPWM5_B EMIF1_D11 XCLKOUT MCANB_TX UARTA_RX OUTPUTXBAR6 ESC_TX1_DATA2 SD4_D4 FSITXC_CLK SD2_D2
GPIO74 EPWM8_A EMIF1_D10 MCANC_TX ESC_TX1_DATA1 SD1_D4 FSITXA_D0 SD2_C2
GPIO75 EPWM8_B EMIF1_D9 SPID_CLK MCANC_RX OUTPUTXBAR16 ESC_TX1_DATA0 SD2_D3
GPIO76 EPWM9_A EMIF1_D8 UARTD_TX MCANE_TX SD4_D4 ESC_PHY_RESETn SD3_C1 FSIRXC_D0 SD2_C3 ESC_GPI17
GPIO77 EPWM9_B EMIF1_D7 UARTD_RX MCANE_RX SD1_D4 ESC_RX0_CLK SD3_D1 FSITXB_D0 SD2_D4
GPIO78 EPWM10_A EMIF1_D6 EPWM11_A MCANF_TX SD4_D4 ESC_RX0_DV SD3_C2 FSITXC_D1 SD2_C4 ESC_GPI18
GPIO79 EPWM10_B EMIF1_D5 ERRORSTS ESC_RX0_ERR SD3_D2 FSITXC_D0 SD2_D1
GPIO80 EPWM11_A EMIF1_D4 ERRORSTS SD1_D4 ESC_RX0_DATA0 SD3_C3 SD2_C1
GPIO81 EPWM11_B EMIF1_D3 ESC_RX0_DATA1 SD3_D3
GPIO82 EPWM12_A EMIF1_D2 ESC_RX0_DATA2 SD3_C2
GPIO83 EPWM12_B EMIF1_D1 ESC_RX0_DATA3 SD3_D2
GPIO84 EPWM12_B EMIF1_D1 EMIF1_CS4n SPIC_PICO UARTA_TX MCANF_RX ESC_TX0_ENA SD3_C2 FSITXC_D1 ESC_RX0_DATA3 ESC_GPO24
GPIO85 EPWM13_A EMIF1_D0 UARTA_RX EMIF1_DQM2 ESC_TX0_CLK SD3_D3
GPIO86 EPWM13_B EMIF1_A13 EMIF1_CAS UARTD_TX ESC_PHY0_LINKSTATUS SD3_C3
GPIO87 EPWM14_A EMIF1_A14 EMIF1_RAS UARTD_RX EMIF1_DQM3 ESC_TX0_DATA0 SD3_D4
GPIO88 EPWM14_B EMIF1_A15 EMIF1_DQM0 EMIF1_DQM1 ESC_TX0_DATA1 SD3_C4
GPIO89 EPWM15_A EMIF1_A16 EMIF1_DQM1 SPID_PTE EMIF1_CAS ESC_TX0_DATA2 SD1_D3 SD4_D1
GPIO90 EPWM15_B EMIF1_A17 EMIF1_DQM2 SPID_CLK EMIF1_RAS ESC_TX0_DATA3 SD1_C3 SD4_C1
GPIO91 EPWM16_A EMIF1_A18 EMIF1_DQM3 SPID_PICO I2CA_SDA MCAND_TX EMIF1_DQM2 SD4_D2 OUTPUTXBAR9
GPIO92 EPWM16_B EMIF1_A19 EMIF1_BA1 SPID_POCI I2CA_SCL MCAND_RX EMIF1_DQM0 FSIRXD_CLK SD4_C2 OUTPUTXBAR10
GPIO93 EPWM17_A EMIF1_BA0 SPID_CLK ESC_TX1_CLK SD4_D3 OUTPUTXBAR11
GPIO94 EPWM17_B SPID_PTE EMIF1_BA1 ESC_TX1_ENA SD4_C3 OUTPUTXBAR12
GPIO95 EPWM18_A ESC_GPO10 SD1_D1 OUTPUTXBAR13
GPIO96 EPWM18_B ESC_GPO11 SD1_C1 OUTPUTXBAR14
GPIO97 ESC_GPI17 SD1_D2 OUTPUTXBAR15
GPIO98 ESC_GPI18 SD1_C2 OUTPUTXBAR16
GPIO99 EPWM8_A EMIF1_DQM3 EMIF1_D17 ESC_GPI21 SD4_D4
GPIO100 EPWM9_A EMIF1_BA1 EMIF1_D24 SPIC_PICO SPIA_PICO SD1_D1 ESC_GPI0 SD4_C4 FSITXA_D0 FSIRXD_D1
GPIO101 EPWM18_A EMIF1_A5 SPIC_POCI ESC_GPI1 FSITXA_D1
GPIO103 EPWM8_B EMIF1_BA0 EMIF1_D3 SPIC_PTE ESC_GPI3 SD4_C4 FSIRXA_D0 ESC_GPO25
GPIO105 EPWM18_B I2CA_SCL ESC_GPI5 SD3_C1 FSIRXA_CLK
GPIO127 EPWM18_A EMIF1_D18 EMIF1_A11 SPID_POCI ESC_GPI27 SD1_C3 FSIRXC_D1 ESC_SYNC0 ESC_GPO26
GPIO219 ERRORSTS EMIF1_A19 EPWM18_B OUTPUTXBAR1 XCLKOUT SD2_C1 ESC_GPI8 ESC_TX0_ENA ESC_GPO27
GPIO220 EPWM6_A SPID_POCI MCANC_TX OUTPUTXBAR2 SD3_D3 ESC_GPI9 ESC_GPO28 X1
GPIO221 EPWM6_B EMIF1_CAS SPID_PTE MCANC_RX OUTPUTXBAR3 SD3_C3 ESC_GPI10 ESC_GPO29 X2
GPIO222 TDI EPWM7_A SPID_PICO UARTB_TX I2CB_SCL OUTPUTXBAR4 SPIC_CLK SD3_D4 ESC_GPI11 ESC_GPO30
GPIO223 TDO EPWM7_B SPID_CLK UARTB_RX I2CB_SDA OUTPUTXBAR5 SPIC_PTE SD3_C4 ESC_GPI12 ESC_GPO31
GPIO224 EPWM12_A EPWM12_B SPIB_POCI MCAND_RX OUTPUTXBAR5 SD4_D2 ADCA_EXTMUXSEL0 ESC_GPO8
GPIO225 EPWM11_B SPIB_PICO I2CB_SDA UARTF_TX OUTPUTXBAR4 SD4_C1 ADCA_EXTMUXSEL1 ESC_GPO9
GPIO226 EPWM10_A SPIA_PTE MCAND_TX UARTF_RX OUTPUTXBAR1 SD1_C3 SD1_D3 ADCA_EXTMUXSEL2 ESC_GPO10
GPIO227 EPWM14_B SPIA_CLK OUTPUTXBAR4 SD2_C2 ADCA_EXTMUXSEL3
GPIO228 EPWM18_A EPWM13_A SPIB_POCI LINB_TX OUTPUTXBAR1 SENT4 SD2_D1
GPIO229 EPWM17_B EPWM12_B SPIB_PICO MCANA_RX SENT3 SD1_C4
GPIO230 EPWM11_A SYNCOUT I2CB_SCL OUTPUTXBAR3 SD4_D1 ADCB_EXTMUXSEL0
GPIO231 EPWM10_B SPIA_PICO MCAND_RX OUTPUTXBAR2 SD1_C3 ADCB_EXTMUXSEL1
GPIO232 EPWM14_A EPWM8_B SPIA_POCI OUTPUTXBAR3 SENT6 SD3_D1 ESC_PHY0_LINKSTATUS ADCB_EXTMUXSEL2 ESC_GPO11
GPIO233 EPWM18_B EPWM13_B LINB_RX OUTPUTXBAR2 SENT5 SD2_C1 ESC_PHY1_LINKSTATUS ADCB_EXTMUXSEL3 ESC_GPO12
GPIO234 EPWM17_A EPWM12_A SPIB_PTE MCANA_TX SENT2 SD1_D4 ESC_GPO13
GPIO235 EPWM9_B SPIB_CLK MCANA_RX SENT1 SD1_C1 ESC_GPO14
GPIO236 EPWM12_B EPWM8_A LINA_RX OUTPUTXBAR6 SD4_C2 ESC_I2C_SDA ADCC_EXTMUXSEL0
GPIO237 EPWM14_A EPWM8_B EPWM17_B LINA_TX I2CA_SDA OUTPUTXBAR7 SD4_D3 ESC_I2C_SCL ADCC_EXTMUXSEL1
GPIO238 EPWM15_B OUTPUTXBAR6 SD1_D3 SD2_C3 ESC_SYNC0 ADCC_EXTMUXSEL2 ESC_GPO15
GPIO239 EPWM16_B LINB_TX I2CA_SCL OUTPUTXBAR8 SD2_C4 ESC_SYNC1 ADCC_EXTMUXSEL3 ESC_GPO16
GPIO240 EPWM14_B SPID_PICO SD4_C3 ESC_LED_RUN ADCD_EXTMUXSEL0
GPIO241 EPWM8_A SPID_CLK SD4_D4 ESC_LED_ERR ADCD_EXTMUXSEL1 ESC_GPO17
GPIO242 SD1_D4 I2CA_SDA OUTPUTXBAR9 SENT1 SD2_D2 ESC_LED_STATE_RUN ADCD_EXTMUXSEL2 ESC_GPO18
GPIO243 EPWM8_B SENT2 SD2_D4 ESC_LED_LINK0_ACTIVE ADCD_EXTMUXSEL3 ESC_GPO19
GPIO244 SPIC_PTE SENT5 SD4_C4 ESC_LED_LINK1_ACTIVE
GPIO245 SPIC_POCI SENT6 SD3_C1 ESC_PHY_RESETn
GPIO246 EPWM16_A SPID_PTE MCANC_RX OUTPUTXBAR7 SD1_D1 ADCE_EXTMUXSEL0 ESC_GPO20
GPIO247 EPWM15_A ERRORSTS SPID_POCI MCANC_RX LINA_TX OUTPUTXBAR5 SD2_D3 ADCE_EXTMUXSEL1 ESC_GPO21
GPIO248 EMIF1_SDCKE SPIC_PICO SENT3 SD1_C2 ESC_LED_RUN ADCE_EXTMUXSEL2 ESC_GPO22
GPIO249 SPIC_CLK SENT4 SD1_D2 ESC_PHY0_LINKSTATUS ADCE_EXTMUXSEL3 ESC_GPO23
AIO160 SD3_C2
AIO161 SD3_D2
AIO162 SD2_C2
AIO163 SD2_D2
AIO164 SD2_C3
AIO165 SD2_D3
AIO166 SD4_C1
AIO167 SD4_D1
AIO168 SD3_C3
AIO169 SD3_D3
AIO170 SD3_C4
AIO171 SD3_D4
AIO172 SD1_C1
AIO173 SD1_D1
AIO174 SD2_C4
AIO175 SD2_D4
AIO176 SD4_C2
AIO177 SD4_D2
AIO178 SD4_C3
AIO179 SD4_D3
AIO180 SD1_C2
AIO181 SD1_D2
AIO182 SD3_C1
AIO183 SD3_D1
AIO184 SD3_C2
AIO185 SD3_D2
AIO186 SD1_C1
AIO187 SD1_D1
AIO188 SD1_C2
AIO189 SD1_D2
AIO190 SD1_C3
AIO191 SD1_D3
AIO192 SD1_C3
AIO193 SD1_D3
AIO194 SD1_C4
AIO195 SD1_D4
AIO196 SD4_C4
AIO197 SD4_D4
AIO198 SD1_C4
AIO199 SD1_D4
AIO200 SD2_C1
AIO201 SD2_D1
AIO202 SD2_C1
AIO203 SD2_D1
AIO204 SD3_C3
AIO205 SD3_D3
AIO206 SD3_C4
AIO207 SD3_D4
AIO208 SD2_C2
AIO209 SD2_D2
AIO210 SD2_C3
AIO211 SD2_D3
AIO212 SD2_C4
AIO213 SD2_D4