The C29 CPU is a VLIW (Very Long
Instruction Word) architecture with a fully protected pipeline. The CPU supports
multiple instruction sizes (16/32/48 bits). The CPU also supports variable
instruction packet size, with each packet able to contain up to eight instructions
that execute in parallel. For example, the CPU architecture can execute up to eight
16-bit instructions in parallel. This is enabled by multiple functional units inside
the CPU which can execute concurrently. A total of 64 working registers, broken into
three different categories (Ax, Dx and Mx Register banks) support the parallel
operations in the CPU. In addition to the working registers, the CPU contains
multiple status registers (DSTS, ESTS and ISTS) which maintain execution-related and
interrupt-context-related information.
Following are the list of C29 CPU
major features:
- Ease of use:
- Byte addressable
CPU.
- Linear and unified memory
map with 4GB address range.
- Fully Protected Pipeline:
9 stage pipeline that prevents writes and reads from same location from
occurring out of order.
- Deterministic execution
and maximum performance without cached memories.
- Improved parallelism:
- Execute from 1 to 8
instructions in parallel.
- Execute fixed-point,
floating-point, and addressing operations in parallel.
- Multiple parallel
functional units.
- Specialized operations to
minimize discontinuities and accelerate decision making code (for
example, if-then-else statements and switch statements).
- Specialized operations
targeting real-time control (for example, trigonometric operations and
multiphase vector translation operations).
- Improved bus
throughput:
- Capable of fetching up to
128-bit instruction packet every cycle.
- Capable of performing
8/16/32/64-bit dual reads and single writes per cycle.
- Improved addressing modes
reduce overhead in accessing memory and peripheral resources.
- Improved pipeline allows
for additional 0-wait memory to be accessible to CPU for max
performance.
- Code efficiency:
- Supports variable length
instruction set (16-bit, 32-bit and 48-bit instructions).
- Rich instruction set
optimizes the most common operations in smallest instructions.
- ASIL-D safety capability with
code isolation in hardware:
- Lock step core capable of
independent execution in split-lock mode (acting as a separate core) or
lock step execution (for redundancy).
- Integrated ECC logic
- Integrated memory
management (MPU) and protection mechanisms in hardware to maximize
MIPS.
- Separate code threads are
fully isolated and protected (including software stacks).
- Enhanced debug and trace
capabilities:
- Specialized data logging
and code flow trace instructions.
- Trace data capable of
being logged in on-chip RAM or exported through serial communication
peripherals.