SNLS564B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHU|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 SPI Host-Side Control Interface

If SPI is used as the host-side communication protocol, the maximum number of FPC202 devices which can share a single SPI bus is technically unlimited. The read and write latency from/to the downstream ports will increase as the length of the SPI chain increases.

SPI does not require each FPC202 to have an address. The FPC202 devices are connected in a daisy-chain fashion as shown in Figure 7-6. The first FPC202 will connect CTRL3 (MOSI) to the host controller’s MOSI signal. CTRL4 (MISO) on the first FPC202 will connect to the subsequent FPC202’s CTRL3 (MOSI) signal and so on until the final FPC202’s CTRL4 (MISO) signal connects back to the host controller’s MISO signal. All FPC202’s will connect CTRL1 (SCK) and CTRL2 (SS_N) to the same SCK and SS_N pin on the host controller. For LED blink synchronization across multiple FPC202 devices, the SPI_LED_SYNC pin should be connected across all FPC202 devices in SPI mode. This is not necessary in I2C mode.

Each FPC202 device in the SPI chain will capture and act upon the command in its shift register when SS_N transitions from low (0) to high (1). The MOSI input is ignored and the MISO output is high impedance whenever SS_N is de-asserted high.

The prior SPI command, address, and data are shifted out on MISO as the current SPI command, address, and data are shifted in on MOSI. In all SPI transactions, the MISO output signal is enabled asynchronously whenever SS_N is asserted low.

GUID-525FBAA2-50CF-48C4-8943-FDA098E163AB-low.gifFigure 7-6 FPC202 Connection Diagram For SPI Mode

The SPI address space for FPC202 applications is designed such that each port being controlled and each logical device address within each port is accessible to the host controller through a unique 12-bit address. For a system with up to N FPC202 devices on a single SPI chain, the full SPI address map is shown in Table 7-7.

Table 7-7 SPI Address Map
FPC202 INSTANCE NUMBERADDRESS RANGE
PORT 0PORT 1FPC202 REGS
PRIMARY DEVICE
Default = 0xA0(1)		SECONDARY DEVICE
Default = 0xA0(1)		PRIMARY DEVICE
Default = 0xA0(1)		SECONDARY DEVICE
Default = 0xA0(1)
00x000 to 0x0FF0x100 to 0x1FF0x400 to 0x4FF0x500 to 0x5FF0x800 to 0x8FF
1
2
–
N
(1) Device addresses are programmable. By default, the device 0 address is 0xA0 and the device 1 address is 0xA2. Request access to the FPC202 Programmer's Guide (SNLU229) here for more details.

In SPI mode, the CTRL4 pin has a driver impedance of 60 Ω (typical). In order to minimize ringing due to the fast edge rate of the driver, it is recommended to match the transmission line characteristic impedance with the driver impedance. A series resistor near the driver pin (CTRL4) may be used to facilitate this impedance matching. If ringing is a concern, the IBIS model provided may be used for simulations.