SNLS564B December 2017 – January 2024 FPC202
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
WTOTAL | Total device power dissipation | VDD1 = VDD2 = 3.3 V, Outputs sourcing maximum current; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 90 | 110 | mW | |
VDD1 = 3.3 V, VDD2 = 2.5 V, Outputs sourcing maximum current; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 100 | 110 | mW | |||
VDD1 = 3.3 V, VDD2 = 1.8 V, Outputs sourcing maximum current; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 100 | 120 | mW | |||
IVDD1 | Current consumption for VDD1 supply | VDD1 = VDD2 = 3.3 V; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 26 | 31 | mA | |
VDD1 = VDD2 = 2.5 V; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 27 | 32 | ||||
VDD1 = 3.3 V, VDD2 = 1.8 V; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 29 | 34 | mA | |||
IVDD2 | Current consumption for VDD2 supply | VDD1 = VDD2 = 3.3 V, Outputs sourcing maximum current; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 0.2 | 0.35 | mA | |
VDD1 = 3.3 V, VDD2 = 2.5 V, Outputs sourcing maximum current; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 0.1 | 0.3 | mA | |||
VDD1 = 3.3 V, VDD2 = 1.8 V, Outputs sourcing maximum current; S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are OFF (Vout = High) | 0.1 | 0.25 | mA | |||
Itotal-idle | Total device supply current consumption in idle mode | 6.5 | mA | |||
LVCMOS I/O DC SPECIFICATIONS | ||||||
VIH | High level input voltage | Applies to S0_IN_A, S0_IN_B, S0_IN_C, S1_IN_A, S1_IN_B, S1_IN_C, PROTOCOL_SEL, and GPIO[3:0] | 2.0 | 3.465 | V | |
Applies to EN | 0.7* VDD2 | VDD2 | ||||
VIL | Low level input voltage | Applies to S0_IN_A, S0_IN_B, S0_IN_C, S1_IN_A, S1_IN_B, S1_IN_C, PROTOCOL_SEL, GPIO[3:0], and EN | –0.3 | 0.8 | V | |
VOH | High level output voltage | Applies to S0_OUT_A, S0_OUT_B, and GPIO[3:0], IOH = –2 mA | 2.8 | 3.465 | V | |
Applies to S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D, IOH = –50 µA | 2.5 | |||||
VOL | Low level output voltage | Applies to S0_OUT_A, S0_OUT_B, and GPIO[3:0], IOL = 2 mA | GND | 0.4 | V | |
Applies to S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D, IOL = 18 mA | GND | 0.4 | ||||
IIH | High level input current | Applies to S0_IN_A, S0_IN_B, S0_IN_C, S1_IN_A, S1_IN_B, S1_IN_C, and GPIO[3:0] | –1 | 1 | µA | |
IIL | Low level input current | Applies to S0_IN_A, S0_IN_B, S0_IN_C, S1_IN_A, S1_IN_B, S1_IN_C | –220 | –170 | µA | |
Applies to GPIO[3:0] | –1 | 1 | µA | |||
tSP-LS | Pulse width of spikes that are suppressed by FPC202 input de-glitch filter on all IN_* low-speed pins | Pulses shorter than min are suppressed, and pulses longer than the max are not suppressed. | 30 | 50 | µs | |
DOWNSTREAM MASTER I2C ELECTRICAL CHARACTERISTICS (MOD_SCL AND MOD_SDA) | ||||||
VOL | Low level output voltage | IOL = 3 mA | GND | 0.4 | V | |
VIL | Low level input voltage | –0.3 | 1.04 | V | ||
VIH | High level input voltage | 2.19 | 3.465 | V | ||
Cb(1) | I2C bus capacitive load | 1.6 kΩ pull-up resistor max | 200 | pF | ||
HOST-SIDE I2C ELECTRICAL CHARACTERISTICS (PROTOCOL_SEL=FLOAT/HIGH) | ||||||
VIH | Input high level voltage | SDA (CTRL2) and SCL (CTRL1) | 0.7* VDD2 | VDD2 | V | |
VIL | Input low level voltage | SDA (CTRL2) and SCL (CTRL1) | 0.3* VDD2 | V | ||
CIN(1) | Input pin capacitance | SDA (CTRL2) and SCL (CTRL1) | 0.5 | 1 | pF | |
VOL | Low level output voltage | SDA (CTRL2) or SCL (CTRL1), IOL = 3 mA | GND | 0.4 | V | |
IL | IL Leakage current | SDA (CTRL2) or SCL (CTRL1), VIN = VDD2 | –1 | 1 | μA | |
Cb(1) | I2C bus capacitive load | 550 | pF | |||
HOST-SIDE SPI ELECTRICAL CHARACTERISTICS (PROTOCOL_SEL=GND) | ||||||
VIH | Input high level voltage | SCK (CTRL1), SS_N (CTRL2), and MOSI (CTRL3) | 0.7* VDD2 | V | ||
VIL | Input low level voltage | SCK (CTRL1), SS_N (CTRL2), and MOSI (CTRL3) | 0.3* VDD2 | V | ||
CIN(1) | Input pin capacitance | SCK (CTRL1), SS_N (CTRL2), and MOSI (CTRL3) | 0.5 | 1 | pF | |
VOH | High level output voltage | MISO (CTRL4) pin, IOH = –4 mA | 0.7* VDD2 | V | ||
VOL | Low level output voltage | MISO (CTRL4) pin, IOL = 4 mA | GND | 0.4 | V | |
IL | Leakage current | MOSI (CTRL3) | –220 | –170 | µA | |
SCK (CTRL1), SS_N (CTRL2), and MISO (CTRL4) | –1 | 1 | μA | |||
CMISO(1) | MISO output capacitive load | MISO (CTRL4) pin | 50 | pF |