SNLS564B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHU|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

  1. Decoupling capacitors should be placed as close to the VDD1/VDD2 pins as possible.
  2. The die attach pad (DAP) should have a low-impedance connection to the nearest GND plane. This is typically accomplished with vias connecting the surface GND plane to inner-layer GND planes. One recommended option is to place 14 vias spaced ≥1 mm apart in a seven by two grid as shown in Figure 8-8.
  3. When placing the FPC202 underneath an SFP or QSFP cage, on the opposite side of the PCB, as shown in Figure 8-8, take note of the SFP/QSFP keep-out areas as well as any keep-out area required for the pressfit assembly tooling.
  4. Pin 32 (CAPL) should have a low-impedance, low-inductance path to a 2.2-µF decoupling capacitor to GND. If space constraints force this capacitor to be placed away from the pin, then a wider metal trace (that is, 20 mil) to the capacitor, utilizing an inner layer if necessary, is recommended.
  5. A GND pin is provided (pin 27) to make it easy to probe GND near the FPC202, especially in applications where the opposite side of the PCB is covered by an SFP or QSFP cage and therefore inaccessible. To maximize the benefit of this probe point, connect this pin to the local GND plane (that is, to the DAP and associated GND vias) through a low-impedance trace. In addition, it may be helpful to route a short trace to a probe point for easy access.