SNLS564B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHU|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 LED Control

The FPC202 uses four sets of outputs, P[1:0]_S0_OUT_C, P[1:0]_S0_OUT_D, P[1:0]_S1_OUT_C, and P[1:0]_S1_OUT_D to drive LEDs associated with the ports under its control. Most SFP and QSFP applications use one yellow and one green LED per port to indicate different link status such as link up, link down, and other link states. Some QSFP applications require one LED per lane, which equals four LEDs per port.

For applications requiring more than four LEDs per port, spare outputs (OUT_* and GPIO) can be used to drive additional LEDs in a mostly-static fashion. The blinking and dimming capabilities available on the S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D pins are not available on the other FPC202 outputs.

LEDs should be connected to the FPC202 in an active-low fashion as shown in Figure 7-1. When the S0_OUT_C, S0_OUT_D, S1_OUT_C, or S1_OUT_D pin drives a low voltage (VOL), the LED is illuminated. When these pins drive a high voltage (VOH), the LED is off. Bi-color LEDs can be connected in a similar fashion, and each LED should have its own current-limiting resistor. The current-limiting resistor value is selected by choosing the desired maximum current through the LED and the corresponding voltage drop from the LED's current vs. voltage plot. The sum of forward voltage drop of the LED, the voltage drop across the series resistor, and the maximum VOL (0.5 V maximum for currents between 2 and 18 mA) is equal to the LED supply voltage. Note that S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D are tri-stated while the device is held in reset (during POR or while the EN pin is low), and are enabled during normal operation and drive a high voltage by default.

GUID-1CCB54EE-637D-43BB-987F-702D57C1AE20-low.gifFigure 7-1 Example Connection Between S0_OUT_C, S0_OUT_D, S1_OUT_C, and S1_OUT_D and Active-Low LEDs

Each port under the FPC202’s control has a set of registers that allow the user to configure each LED into one of the following states:

  • ON
  • OFF
  • PWM (ON with programmable intensity)
  • BLINK (with programmable blink duty cycle, frequency, and ON intensity)
LED blinking is configured by setting an on and an off time. Each of these times is configured separately and have a minimum value of 2.5 ms and a maximum value of 637.5 ms for a maximum blinking period of 1.275 seconds. The pulse width modulation (PWM) duty cycle has 256 settings where 0 is completely off, and 255 is maximum brightness. Note that the PWM is 0 by default and must be configured for the LEDs to be visible in BLINK or PWM modes.

LED blinking can be synchronized across both ports under the FPC202’s control, and it can be synchronized across all ports in the system which are under the control of an FPC202. For SPI, cross-device synchronization utilizes the SPI_LED_SYNC pin. One device is configured to forward its internal LED clock to this pin, and all other devices are configured to receive an external LED clock on this pin. For I2C, the first device in the CTRL4 to CTRL3 pin daisy chain is configured to output its internal LED clock to the CTLR4 pin. All other devices are configured to receive an external LED clock from the CTRL3 pin and to output the clock to the CTRL4 pin.