SNLS564B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHU|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DOWNSTREAM MASTER I2C SWITCHING CHARACTERISTICS
fSCLSCL clock frequencyApplies to standard-mode I2C, 100 kHz6683100kHz
Applies to fast-mode I2C, 400 kHz264332400kHz
tLOW-SCLSCL clock pulse width low period1.3μs
tHIGH-SCLSCL clock pulse width high period0.6μs
tBUFTime bus free before new transmission startsBetween STOP and START and between ACK and RESTART20μs
tHD-STAHold time START operation0.6μs
tSU-STASetup time START operation0.6μs
tHD-DATData hold time0μs
tSU-DATData setup time0μs
tRSCL and SDA rise time100 KHz operation. From VIL (Max) - 0.15 V to VIH (Min) + 0.15 V.300ns
SCL and SDA rise time100 KHz operation. From VIL (Max) - 0.15 V to VIH (Min) + 0.15 V.300
tFSCL and SDA fall time100 KHz operation. From VIH (Min) + 0.15 V to VIL (Max) - 0.15 V.300ns
SCL and SDA fall time400 KHz operation. From VIH (Min) + 0.15 V to VIL (Max) - 0.15 V.300
tSU-STOSTOP condition setup time0.6μs
tSP-I2C(1)Pulse width of spikes that are suppressed by FPC202 input filter050ns
(1) These parameters are not production tested.