SNLS582C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2.1 SPI Frame Structure

Each SPI transaction to a single FPC402 device is 29 bits long and is framed by the assertion of SS_N (CTRL2) low. The MOSI (CTRL3) input is ignored and the MISO (CTRL4) output is high impedance whenever SS_N is deasserted high. The prior SPI command, address, and data are shifted out on MISO as the current SPI command, address, and data are shifted in on MOSI. In all SPI transactions, the MISO output signal is enabled asynchronously whenever SS_N is asserted low.

Table 8-8 shows the structure of a SPI frame. Figure 8-7 shows an example implementation, including the internal SPI registers, for two FPC402 devices.

Table 8-8 SPI Frame Structure
BITFIELDDESCRIPTION
28R/W

0: Write command

1: Read command

This is the first bit shifted in on the MOSI input.

27:16ADDR[11:0]12-bit address field. See Table 8-7.
15DATA[15]Busy flag. For read operations, a 1 means the downstream port is busy. For write operations, DATA[15] is a don't care.
14DATA[14]Don't care.
13DATA[13]NACK received flag. A 1 means the FPC402 has received a NACK from the downstream port.
12DATA[12]Reject flag. A 1 means the FPC402 has rejected the previous command because it is busy servicing a prior command.
11:8DATA[11:8]Don't care.
7:0DATA[7:0]

8-bit data field.

DATA[0] is the last bit shifted in on the MOSI input.

GUID-A732C8D8-00F4-46E1-BF71-CBC1C4B1C00B-low.gifFigure 8-7 Example SPI Implementation for Two FPC402 Devices
GUID-726293DB-6B46-47DB-83DE-DCE1110ABE58-low.gifFigure 8-8 Generic SPI Transaction

The timing specification for an SPI transaction is described inFigure 8-9.

GUID-8E3AA777-C514-4124-A3FB-5AAC86E7D537-low.gifFigure 8-9 SPI Timing Diagram