SNLS582C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.2 Detailed Design Procedure

The design procedure for SFP/QSFP applications is as follows:

  1. Determine the total number of ports in the system, Nports, which require management through an FPC402 device. The minimum number of FPC402 devices required to support Nports is ceiling{Nports÷4}.
  2. Determine which host-side control interface will be used to manage all FPC402 devices and all ports: I2C or SPI.
  3. For I2C applications:
    1. Up to 14 FPC402 devices can share a single host-side I2C control bus. If more than 14 FPC402 devices are used, then more than one I2C control bus will be required.
    2. Take care to ensure the I2C clock (SCL) and data (SDA) lines do not exceed the maximum bus capacitance defined in Section 7.5. The bus capacitance will consist of the pin capacitance from each device connected plus the trace capacitance.
    3. Make sure appropriate pullup resistors are selected for the I2C clock (SCL) and data (SDA) lines.
  4. For SPI applications:
    1. When using SPI for host-side communications, technically there is no limit to the number of FPC402 devices which can exist on the SPI chain. However, the user must be aware that for SPI communication, skew is introduced between the SCK and MISO lines due to the propagation delay of the data through all of the devices and trace and then back to the host. It is up to the user to ensure that SPI timings of the host are met after any skew due to propagation delay.
    2. Take care to ensure the SPI clock (SCK) and data (MOSI and MISO) lines do not exceed the maximum bus capacitance defined in Section 7.5. The bus capacitance will consist of the pin capacitance from each device connected plus the trace capacitance.
  5. Route the low-speed inputs (IN_*[3:0]), outputs (OUT_*[3:0]), and I2C signals (MOD_SCL[3:0] / MOD_SDA[3:0]) from the FPC402 to the corresponding port, keeping all the signals for a given port grouped together. For example, if FPC402 port 2 is being used to control QSFP port 7, then all of low-speed signals of the QSFP port 7s , LED signals, and I2C signals must connect to FPC402 pins IN_*[2], OUT_*[2], and MOD_SCL[2]/MOD_SDA[2].
  6. Use the spare GPIO[3:0] signals to control miscellaneous functions on the board, like enabling and disabling a power switch.
  7. For applications requiring hot-plug between the FPC402 and the host controller, control the FPC402 enable signal (EN, pin 22) such that EN is deasserted low until VDD2 and the host-side control interface (I2C or SPI) is fully connected and stable.