SLLSES1D December   2015  – September 2020 HD3SS3220

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Device
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DFP/Source – Downstream Facing Port
      2. 7.3.2  UFP/Sink – Upstream Facing Port
      3. 7.3.3  DRP – Dual Role Port
      4. 7.3.4  Cable Orientation and Mux Control
      5. 7.3.5  Type-C Current Mode
      6. 7.3.6  Accessory Support
      7. 7.3.7  Audio Accessory
      8. 7.3.8  Debug Accessory
      9. 7.3.9  VCONN support for Active Cables
      10. 7.3.10 I2C and GPIO Control
      11. 7.3.11 HD3SS3220 V(BUS) Detection
      12. 7.3.12 VDD5 and VCC33 Power-On Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Dead Battery
      4. 7.4.4 Shutdown Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
      2. 7.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]
      3. 7.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
      4. 7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
      5. 7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application, DRP Port
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application, DFP Port
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Typical Application, UFP Port
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Suggested PCB Stackups
      2. 9.1.2 High-Speed Signal Trace Length Matching
      3. 9.1.3 Differential Signal Spacing
      4. 9.1.4 High-Speed Differential Signal Rules
      5. 9.1.5 Symmetry in the Differential Pairs
      6. 9.1.6 Via Discontinuity Mitigation
      7. 9.1.7 Surface-Mount Device Pad Discontinuity Mitigation
      8. 9.1.8 ESD/EMI Considerations
    2. 9.2 Layout
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

MINNOMMAXUNIT
I2C (SDA, SCL)
tSU:DATData setup time100ns
tHD:DATData setup time10ns
tSU;STASet-up time, SCL to start condition0.6µs
tHD,STAHold time,(repeated) start condition to SCL0.6µs
tSU:STOSet up time for STOP condition0.6µs
tVD;DATData valid time0.9µs
tVD;ACKData valid acknowledge time0.9µs
tBUFBus free time between a STOP and START condition1.3µs
fSCLSCL clock frequency; I2C mode for local I2C control400ns
trRise time of both SDA and SCL signals300ns
tfFall time of both SDA and SCL signals300ns
CBUS_100KHZTotal capacitive load for each bus line when operating at ≤ 100 KHz400pF
CBUS_400KHZTotal capacitive load for each bus line when operating at 400 KHz.100pF
SS MUX
tPDSwitch propagation delay See Figure 6-380ps
tSW_ONSwitching time DIR-to-Switch ON See Figure 6-20.5µs
tSW_OFFSwitching time DIR-to-Switch OFF See Figure 6-20.5µs
tSK_INTRAIntra-pair output skew See Figure 6-35ps
tSK_INTERInter-pair output skew See Figure 6-320ps
Power-On Timings
tENnCC_HI ENn_CC high after both VDD5 and VCC33 supplies are stable. Refer to Figure 7-3. 2 ms
tVDD5V_PG VDD5 stable before VCC33. Refer to Figure 7-2. 2 ms
GUID-BFD15B47-64EC-473C-BB4E-EABCB70B3C01-low.svgFigure 6-1 Test Setup
GUID-F6CC9403-8511-46BA-8519-2A1E2BD63219-low.svgFigure 6-2 Switch On and Off Timing Diagram
GUID-FD4FD955-F378-45EB-8BA7-5C91CE2A32A9-low.svgFigure 6-3 Timing Diagrams and Test Setup