SLLSEC4B June   2013  – August 2016 HVDA551-Q1 , HVDA553-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristic
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 Using the HVDA553 With Split Termination
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant State Time Out
        2. 8.3.3.2 Thermal Shutdown
        3. 8.3.3.3 Undervoltage Lockout or Unpowered Device
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode With RXD Wake-Up Request
        1. 8.4.3.1 RXD Wake-Up Request Lockout for Bus-Stuck Dominant Fault (HVDA551)
      4. 8.4.4 Driver and Receiver Function Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level in Low-Power Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Loop Propagation Delay
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VCC Supply voltage –0.3 6 V
VIO I/O supply voltage –0.3 6 V
Voltage at bus terminals (CANH, CANL) –27 40 V
IO Receiver output current (RXD) 20 mA
VI Voltage input (TXD, STB, S) HVDA55x –0.3 6 and VI ≤ VIO + 0.3 V
HVDA553 –0.3 6
TJ Operating virtual-junction temperature –40 150 °C
Tstg Storage temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to the ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) All pins except 6 and 7 ±4000 V
Pins 6 and 7(2) ±12000
Charged-device model (CDM)(3) ±1000
IEC 61000-4-2 according to IBEE CAN EMC test specification(4) Pins 6, 7 to 2 ±7000
ISO 7637 transients according to IBEE CAN EMC test specification(5) Pulse 1 –100
Pulse 2a 75
Pulse 3a –150
Pulse 3b 100
(1) HBM tested in accordance with AEC-Q100-002.
(2) HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.
(3) CDM tested in accordance with AEC-Q100-011.
(4) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system-level configurations lead to different results.
(5) ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system level configurations lead to different results.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 4.68 5.33 V
VIO I/O supply voltage 3 5.33 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
VIH High-level input voltage, TXD, STB (for HVD553, VIO = VCC) 0.7 × VIO VIO V
VIL Low-level input voltage, TXD, STB (for HVD553, VIO = VCC) 0 0.3 × VIO V
VID Differential input voltage, bus (between CANH and CANL) –6 6 V
IOH High-level output current, RXD –2 mA
IOL Low-level output current, RXD 2 mA
TA Operating ambient free-air temperature (see Thermal Information) –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) HVDA55x-Q1 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance Low-K thermal resistance 140 °C/W
High-K thermal resistance 112
RθJC(top) Junction-to-case (top) thermal resistance 56 °C/W
RθJB Junction-to-board thermal resistance 50 °C/W
ψJT Junction-to-top characterization parameter 13 °C/W
ψJB Junction-to-board characterization parameter 55 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, HVDA553 VIO = VCC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
HVDA551 SUPPLY
ICC 5-V supply current Standby mode (HVDA551 only), STB at VIO, VCC = 5.33 V, VIO = 3 V, TXD at VIO (2) 5 µA
Normal mode (dominant), TXD at 0 V,
60-Ω load, STB at 0 V		 50 70 mA
Normal mode (recessive), TXD at VIO, no load, STB at 0 V 6.75 10
IIO I/O supply current Standby mode (HVDA551 only), STB at VIO , VCC = 5.33 V or 0 V, RXD floating, TXD at VIO, TA = –40°C, 25°C, 125°C(3) 6.5 15 µA
Normal mode (dominant), VCC = 5.33 V, RXD floating, TXD at 0 V 85 300
Normal mode (recessive), VCC = 5.33 V, RXD floating, TXD at VIO 70 300
UVVCC Undervoltage detection On VCC for forced standby mode 3.2 3.6 4 V
VHYS(UVVCC) Hysteresis voltage For undervoltage detection on UVVCC for standby mode 200 mV
UVVIO Undervoltage detection On VIO for forced standby mode 1.9 2.45 2.95 V
VHYS(UVVIO) Hysteresis voltage For undervoltage detection on UVVIO for forced standby mode 130 mV
HVDA553 SUPPLY
ICC 5-V supply current Standby mode (HVDA553 only), STB at VCC, VCC = 5.33 V, TXD at VCC(2) 12 µA
Normal mode (dominant), TXD at 0 V, 60-Ω load, STB at 0 V 50 70 mA
Normal mode (recessive), TXD at VCC, no load, STB at 0 V 6.75 10
UVVCC Undervoltage detection On VCC for forced standby mode 3.2 3.6 4 V
VHYS(UVVCC) Hysteresis voltage For undervoltage detection on UVVCC for standby mode 200 mV
DRIVER
VO(D) Bus output voltage (dominant) CANH, VI = 0 V, STB at 0 V, RL = 60 Ω, see Figure 2 and Figure 16 2.9 4.5 V
CANL, VI = 0 V, STB at 0 V, RL = 60 Ω, see Figure 2 and Figure 16 0.8 1.75
VO(R) Bus output voltage (recessive) VI = VIO, VIO = 3 V, STB at 0 V, RL = 60 Ω, see Figure 2 and Figure 16 2 2.5 3 V
VO(STBY) Bus output voltage Standby mode (HVDA551 only), STB at VIO,
RL = 60 Ω, see Figure 2 and Figure 16 		–0.1 0.1 V
VOD(D) Differential output voltage (dominant) VI = 0 V, RL = 60 Ω, STB at 0 V, see Figure 2, Figure 16, and Figure 3 1.5 3 V
VI = 0 V, RL = 45 Ω, STB at 0 V, see Figure 2, Figure 16, and Figure 3 1.4 3
VOD(R) Differential output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω, see Figure 2 and Figure 16 –0.012 0.012 V
VI = 3 V, STB at 0 V, no load –0.5 0.05
VSYM Output symmetry (dominant or recessive) VO(CANH) + VO(CANL), STB at 0 V, RL = 60 Ω, see Figure 12 0.9 × VCC VCC 1.1 × VCC V
VOC(SS) Steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, see Figure 8 2 2.5 3 V
ΔVOC(SS) Change in steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, see Figure 8 50 mV
IOS(SS)_DOM Short-circuit steady-state output current, dominant VCANH = 0 V, CANL open, TXD = low, see Figure 11 –100 mA
VCANL = 32 V, CANH open, TXD = low, see Figure 11 100
IOS(SS)_REC Short-circuit steady-state output current, recessive –20 V ≤ VCANH ≤ 32 V, CANL open,
TXD = high, see Figure 11 		–10 10 mA
–20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, see Figure 11 		–10 10
CO Output capacitance See receiver input capacitance
RECEIVER
VIT+ Positive-going input threshold voltage Normal mode, STB at 0 V, see Table 1 800 900 mV
VIT– Negative-going input threshold voltage Normal mode, STB at 0 V, see Table 1 500 650 mV
Vhys Hysteresis voltage VIT+ – VIT– 125 mV
VIT(STBY) Input threshold voltage HVDA551 only, standby mode, STB at VIO 400 1150 mV
II(OFF_LKG) Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC at 0 V, VIO at 0 V, TXD at 0 V 3 µA
CI Input capacitance to ground (CANH or CANL) HVDA551: TXD at VIO, VIO at 3.3 V;
HVDA553: TXD at VCC, VI = 0.4 sin (4E6πt) + 2.5 V		 13 pF
CID Differential input capacitance HVDA551: TXD at VIO, VIO at 3.3 V;
HVDA553: TXD at VCC, VI = 0.4 sin(4E6πt)		 5 pF
RID Differential input resistance HVDA551: TXD at VIO, VIO = 3.3 V, STB at 0 V; HVDA553: TXD at VCC, STB at 0 V 29 80 kΩ
RIN Input resistance (CANH or CANL) HVDA551: TXD at VIO, VIO = 3.3 V, STB at 0 V; HVDA553: TXD at VCC, STB at 0 V 14.5 25 40 kΩ
RI(M) Input resistance matching [1 – RIN(CANH) / RIN(CANL))] × 100%,
V(CANH) = V(CANL) 		–3% 0% 3%
TXD PIN
VIH High-level input voltage HVD553: VIO = VCC 0.7 × VIO V
VIL Low-level input voltage HVD553: VIO = VCC 0.3 × VIO V
IIH High-level input current HVDA551: TXD at VIO; HVDA553: TXD at VCC –2 2 µA
IIL Low-level input current TXD at 0 V –100 –7 µA
RXD PIN
VOH High-level output voltage HVD553: VIO = VCC, IO = –2 mA, see Figure 6 0.8 × VIO V
VOL Low-level output voltage HVD553: VIO = VCC, IO = 2 mA, see Figure 6 0.2 × VIO V
STB PIN
VIH High-level input voltage HVD553: VIO = VCC 0.7 × VIO V
VIL Low-level input voltage HVD553: VIO = VCC 0.3 × VIO V
IIH High-level input current HVDA551: STB at VIO; HVDA553: STB at VCC –2 2 µA
IIL Low-level input current STB at 0 V –20 µA
SPLIT PIN (HVDA553 ONLY)
VO Output voltage –500 µA < IO < 500 µA 0.3 × VCC 0.5 × VCC 0.7 × VCC V
IO(STB) Leakage current Standby mode, STB at VCC, –12 V ≤ IO ≤ 12 V –5 5 µA
POWER DISSIPATION AND THERMAL SHUTDOWN
PD Average power dissipation VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at
RXD = 15 pF		 140 mW
VCC = 5.33 V, VIO = VCC, TJ = 130°C,
RL = 60 Ω , STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF		 215
Thermal shutdown temperature 185 °C
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
(2) The VCC supply is not required during standby mode so in the application ICC in standby mode may be zero. If the VCC supply remains, then ICC is per specification with VCC.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
PROPAGATION TIME (LOOP TIME TXD to RXD)
tPROP(LOOP1) Total loop delay 1 Driver input (TXD) to receiver output (RXD), recessive to dominant, see Figure 9, STB at 0 V 70 230 ns
tPROP(LOOP2) Total loop delay 2 Driver input (TXD) to receiver output (RXD), dominant to recessive, see Figure 9, STB at 0 V 70 230
DRIVER
tPLH Propagation delay time,
low-to-high level output		 STB at 0 V, see Figure 4 65 ns
tPHL Propagation delay time,
high-to-low level output		 STB at 0 V, see Figure 4 50 ns
tR Differential output signal rise time STB at 0 V, see Figure 4 25 ns
tF Differential output signal fall time STB at 0 V, see Figure 4 55 ns
tEN Enable time from standby or silent mode to normal mode, dominant See Figure 7 30 µs
t(DOM)(2) Dominant time-out See Figure 10 1200 2000 2800 µs
RECEIVER
tPLH Propagation delay time,
low-to-high-level output		 STB at 0 V , see Figure 6 95 ns
tPHL Propagation delay time,
high-to-low-level output		 STB at 0 V , see Figure 6 60 ns
tR Output signal rise time STB at 0 V , see Figure 6 13 ns
tF Output signal fall time STB at 0 V , see Figure 6 10 ns
tBUS Dominant time HVDA551 only, required on bus for wake-up from standby, STB at VIO, see Figure 18 and Figure 19 1.5 5 µs
tCLEAR Recessive time HVDA551 only, on the bus to clear the standby mode receiver output (RXD) if standby mode is entered while bus is dominant, STB at VIO, see Figure 18 and Figure 19 1.5 5 µs
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
(2) The TXD dominant time out (t(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t(DOM), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(DOM) = 11 bits / 300 µs = 37 kbps

6.7 Typical Characteristic

VIO = 5 V, STB = 0 V, Rl = 60 Ω, CL= open, RCM = open, TJ = 25°C (unless otherwise noted)
HVDA551-Q1 HVDA553-Q1 C003_SLLSEC4.png Figure 1. Vod vs VCC for HVDA55x