SBOS977A March   2019  – May 2021 INA302-Q1 , INA303-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Current Sensing
      2. 7.3.2 Out-of-Range Detection
      3. 7.3.3 Alert Outputs
        1. 7.3.3.1 Setting Alert Thresholds
          1. 7.3.3.1.1 Resistor-Controlled Current Limit
            1. 7.3.3.1.1.1 Resistor-Controlled Current Limit: Example
          2. 7.3.3.1.2 Voltage-Source-Controlled Current Limit
        2. 7.3.3.2 Hysteresis
    4. 7.4 Device Functional Modes
      1. 7.4.1 Alert Operating Modes
        1. 7.4.1.1 Transparent Output Mode
        2. 7.4.1.2 Latch Output Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting a Current-Sensing Resistor (RSENSE)
        1. 8.1.1.1 Selecting a Current-Sensing Resistor: Example
      2. 8.1.2 Input Filtering
      3. 8.1.3 Using the INA30x-Q1 With Common-Mode Transients Greater Than 36 V
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Related Links
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Latch Output Mode

The comparators are set to latch output mode when the corresponding LATCHx pin is pulled high. Some applications do not continuously monitor the state of the ALERTx pins as described in the Section 7.4.1.1 section. For example, if the device is set to transparent output mode in an application that only polls the state of the ALERTx pins periodically, then the transition of the ALERTx pins can be missed when the out-of-range condition is not present during one of these periodic polling events. Latch output mode allows the output of the comparators to latch the output of the range condition so that the transition of the ALERTx pins is not missed when the status of the comparator ALERTx pins is polled.

The difference between latch mode and transparent mode is how the alert output responds when an overcurrent condition is removed. In transparent mode (LATCH1, LATCH2 = low), when the differential input signal drops to within normal operating range, the ALERTx pin returns to the default high setting to indicate that the overcurrent event has ended.

In latch mode (LATCHx = high), when an out-of-range condition is detected and the corresponding ALERTx pin is pulled low; the ALERTx pin does not return to the default high state when the out-of-range condition is removed. In order to clear the alert, the corresponding LATCHx pin must be pulled low for at least 100 ns. Pulling the LATCHx pins low allows the corresponding ALERTx pin to return to the default high level, provided the out-of-range condition is no longer present. If the out-of-range condition is still present when the LATCHx pins are pulled low, then the corresponding ALERTx pin remains low. The ALERTx pins can be cleared (reset to high) by toggling the corresponding LATCHx pin when the alert condition is detected by the system controller.

The latch and transparent modes are illustrated in Figure 7-6. As illustrated in this figure, at time t1, the current-sense amplifier exceeds the limit threshold. During this time the LATCH1 pin is toggled with no affect to the ALERT1 output. The state of the LATCH1 pin only matters when the output of the current-sense amplifier returns to the normal operating region, as shown at t2. At this time the LATCH1 pin is high and the overcurrent condition is latched on the ALERT1 output. As shown in the time interval between t2 and t3, the latch condition is cleared when the LATCHx pin is pulled low. At time t4, the LATCH1 pin is already pulled low when the amplifier output drops below the limit threshold for the second time. The device is set to transparent mode at this point and the ALERT1 pin is pulled back high as soon as the output of the current-sense amplifier drops below the alert threshold.

GUID-5E646C83-2411-4309-9CBC-918C2DA6C594-low.gifFigure 7-6 Transparent vs. Latch Mode