SBOS792A August   2017  – January 2018 INA828

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      INA828 Simplified Internal Schematic
      2.      Typical Distribution of Input Offset Voltage Drift
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Setting the Gain
        1. 7.3.1.1 Gain Drift
      2. 7.3.2 EMI Rejection
        1. Table 2. INA828 EMIRR for Frequencies of Interest
      3. 7.3.3 Input Common-Mode Range
      4. 7.3.4 Input Protection
      5. 7.3.5 Operating Voltage
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Reference Terminal
    2. 8.2 Input Bias Current Return Path
    3. 8.3 PCB Assembly Effects on Precision
    4. 8.4 Typical Application
      1. 8.4.1 Design Requirements
      2. 8.4.2 Detailed Design Procedure
      3. 8.4.3 Application Curves
    5. 8.5 Other Application Examples
      1. 8.5.1 Resistance Temperature Detector Interface
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Reference Terminal

The output voltage of the INA828 is developed with respect to the voltage on the reference terminal, REF. Often, in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-supply operation, offsetting the output signal to a precise mid-supply level is useful (for example, 2.5 V in a 5-V supply environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the output so that the INA828 can drive a single-supply ADC.

The voltage source applied to the reference terminal must have a low output impedance. As illustrated in Figure 61, any resistance at the reference terminal (shown as RREF in Figure 61) is in series with one of the internal 40-kΩ resistors.

INA828 ai_D001_SBOS792.gifFigure 61. Parasitic Resistance Shown at the Reference Terminal

The parasitic resistance at the reference terminal, RREF, creates an imbalance in the 4 resistors of the internal difference amplifier, resulting in degraded common-mode rejection ratio (CMRR). Figure 62 shows the degradation in CMRR of the INA828 for increasing resistance at the reference terminal. For the best performance, keep the source impedance to the REF terminal, RREF, below 5 Ω.

INA828 ai_C001_SBOS792.pngFigure 62. The Effect of Increasing Resistance at the Reference Terminal

Voltage reference ICs are an excellent option for providing a low-impedance voltage source for the reference terminal. However, if a resistor voltage divider is used to generate a reference voltage, it must be buffered by an op amp as shown in Figure 63 to avoid CMRR degradation.

INA828 ai_D002_SBOS792.gifFigure 63. Using an Op Amp to Buffer Reference Voltages