SLLSEQ0C august   2015  – may 2023 ISO5852S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pulldown
      3. 9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
      4. 9.3.4 Soft Turnoff, Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5852S Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, POD-max

The ISO5852S maximum-allowed total power consumption of PD = 251 mW consists of the total input power, PID, the total output power, POD, and the output power under load, POL:

Equation 1. PD = PID + POD + POL

With:

Equation 2. PID = VCC1-max × ICC1-max = 5.5 V × 4.5 mA = 24.75 mW

and:

Equation 3. POD = (VCC2 – VEE2) × ICC2-max = (15 V – [–8 V]) × 6 mA = 138 mW

then:

Equation 4. POL = PD – PID – POD = 251 mW – 24.75 mW – 138 mW = 88.25 mW

In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety of parameters:

Equation 5. GUID-2A8E2CFB-9273-42F3-AD76-5207AB3ED559-low.gif

where

  • fINP = signal frequency at the control input IN+
  • QG = power device gate charge
  • VCC2 = positive output supply with respect to GND2
  • VEE2 = negative output supply with respect to GND2
  • ron-max = worst case output resistance in the on-state: 4 Ω
  • roff-max = worst case output resistance in the off-state: 2.5 Ω
  • RG = gate resistor

When RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 10-9 shows a simplified output stage model for calculating POL-WC.

GUID-46953FFA-FA3D-432F-B7B4-8F7CB1D5FFD5-low.gif Figure 10-9 Simplified Output Model for Calculating POL-WC