SLLSFX1 September   2024 ISO6163

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5V Supply (±10%)
    10. 5.10 Supply Current Characteristics—5V Supply (±10%)
    11. 5.11 Electrical Characteristics—3.3V Supply (±10%)
    12. 5.12 Supply Current Characteristics—3.3V Supply (±10%)
    13. 5.13 Electrical Characteristics—2.5V Supply (Minimum)
    14. 5.14 Supply Current Characteristics—2.5V Supply  (Minimum)
    15. 5.15 Switching Characteristics—5V Supply (±10%)
    16. 5.16 Switching Characteristics—3.3V Supply (±10%)
    17. 5.17 Switching Characteristics—2.5V Supply (Minimum)
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
      1. 5.19.1 Typical Characteristics: Supply Current ACTIVE state
      2. 5.19.2 Typical Characteristics: High-Speed Channels (ACTIVE state)
      3. 5.19.3 Typical Characteristics: Supply Current STANDBY State
      4. 5.19.4 Typical Characteristics: Low-Speed Control Channels (ACTIVE and STANDBY States)
      5. 5.19.5 Typical Characteristics: Undervoltage Threshold
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Block Diagram
      2. 7.1.2 Feature Description
    2. 7.2 High-Speed Data Channels: A, B, E and F
    3. 7.3 Low-Speed Control Channels With Automatic Enable: C and D
      1. 7.3.1 Low-Speed Control Channels: Timing and Level Details for Automatic Enable
      2. 7.3.2 Low-Speed Control Channels: Considerations if Used for Data
      3. 7.3.3 Low-Speed Control Channels: Considerations During Power Up and Device Reset Events
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)

8.1 Application Information

The ISO6163 devices are high-performance, six-channel digital isolators. These devices come with 4 high-speed channels and two low-speed control channels with automatic enable controlling the high-speed outputs in normal or low-power modes. The ISO6163 devices use single-ended CMOS-logic switching technology. The supply voltage range is from 2.5V to 5.5V for both supplies, VCC1 and VCC2. Since an isolation barrier separates the two sides, each side can be sourced independently with any voltage within recommended operating conditions allowing the device to provide level shifting in addition to isolation. As an example, supplying the ISO6163 VCC1 with 3.3V (which is within 2.5V to 5.5V) and VCC2 with 5V (which is also within 2.5V to 5.5V) is possible. When designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, MCU or FPGA), and a data converter or a line transceiver, regardless of the interface type or standard.