SLLSFX1 September   2024 ISO6163

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5V Supply (±10%)
    10. 5.10 Supply Current Characteristics—5V Supply (±10%)
    11. 5.11 Electrical Characteristics—3.3V Supply (±10%)
    12. 5.12 Supply Current Characteristics—3.3V Supply (±10%)
    13. 5.13 Electrical Characteristics—2.5V Supply (Minimum)
    14. 5.14 Supply Current Characteristics—2.5V Supply  (Minimum)
    15. 5.15 Switching Characteristics—5V Supply (±10%)
    16. 5.16 Switching Characteristics—3.3V Supply (±10%)
    17. 5.17 Switching Characteristics—2.5V Supply (Minimum)
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
      1. 5.19.1 Typical Characteristics: Supply Current ACTIVE state
      2. 5.19.2 Typical Characteristics: High-Speed Channels (ACTIVE state)
      3. 5.19.3 Typical Characteristics: Supply Current STANDBY State
      4. 5.19.4 Typical Characteristics: Low-Speed Control Channels (ACTIVE and STANDBY States)
      5. 5.19.5 Typical Characteristics: Undervoltage Threshold
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Block Diagram
      2. 7.1.2 Feature Description
    2. 7.2 High-Speed Data Channels: A, B, E and F
    3. 7.3 Low-Speed Control Channels With Automatic Enable: C and D
      1. 7.3.1 Low-Speed Control Channels: Timing and Level Details for Automatic Enable
      2. 7.3.2 Low-Speed Control Channels: Considerations if Used for Data
      3. 7.3.3 Low-Speed Control Channels: Considerations During Power Up and Device Reset Events
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)

5.15 Switching Characteristics—5V Supply (±10%)

VCC1 = VCC2 = 5V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time Channels A, B, E, and F. See Figure 6-1 9 12 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 1 ns
tPLH, tPHL Propagation delay time Channels C and D. See Figure 6-1 9 12 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 1 ns
tsk(o) Channel-to-channel output skew time(2) Channels A and B or E and F (consecutive  channels in active mode) 1 ns
tsk(pp) Part-to-part skew time(3) 3 ns
tr Output signal rise time See Figure 6-1 2.0 3.5 ns
tf Output signal fall time 2.0 3.5 ns
tLP_EN STANDBY State (low power) enable delay time Time required transition to STANDBY state once channels C and D are in the inactive and HIGH states. See Figure 6-2 700 1000 1400 ms
tAMS ACTIVE sample time (portion of tLP_EN), either C or D going LOW ACTIVE sample deglitch time for STANDBY state enable delay time.   See Figure 6-2 10 28 µs
tLPN STANDBY to ACTIVE (Low power to normal) transition time 20 52 µs
tPU_HS_CH Time from UVLO to valid output data on channels A, B, E, and F 120 µs
tPU_LS_CH Time from UVLO to valid output data on channels C and D 100 µs
tDO Default output delay time from input power loss Measured from the time VCC goes below 2.2V if the remaining device signals require normal mode operation. See Figure 6-3 13.5 µs
TIE Time Interval Error Channels A, B, E, and F. 216 – 1 PRBS data at 50Mbps 0.08 2 ns
Channels C and D. 216 – 1 PRBS data at 4Mbps 0.12 2 ns
tJIT(RJ) Random jitter 1 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.