6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
|
MIN |
MAX |
UNIT |
|
Supply voltage(2) |
VCC1, VCC2 |
–0.5 |
6 |
V |
|
Voltage |
INx, OUTx, ENx |
–0.5 |
VCC + 0.5(3) |
V |
IO |
Output current |
–15 |
15 |
mA |
TJ |
Maximum junction temperature |
|
150 |
°C |
Tstg |
Storage temperature |
–65 |
150 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human-body model (HBM), per AEC Q100-002(1) |
±4000 |
V |
Charged-device model (CDM), per AEC Q100-011 |
±1500 |
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
|
MIN |
NOM |
MAX |
UNIT |
VCC1, VCC2 |
Supply voltage |
2.7 |
|
5.5 |
V |
IOH |
High-level output current |
VCC ≥ 3 V |
–4 |
|
|
mA |
VCC < 3 V |
–2 |
|
|
IOL |
Low-level output current |
|
|
4 |
mA |
VIH |
High-level input voltage |
2 |
|
5.5 |
V |
VIL |
Low-level input voltage |
0 |
|
0.8 |
V |
tui |
Input pulse duration |
VCC ≥ 4.5 V |
20 |
|
|
ns |
VCC < 4.5 V |
25 |
|
|
1 / tui |
Signaling rate |
VCC ≥ 4.5 V |
0 |
|
50 |
Mbps |
VCC < 4.5 V |
0 |
|
40 |
TJ |
Junction temperature |
|
|
136 |
°C |
TA |
Ambient temperature |
–55 |
25 |
125 |
°C |
6.4 Thermal Information
THERMAL METRIC(1) |
ISO7142CC-Q1 |
UNIT |
DBQ (SSOP) |
16 PINS |
RθJA |
Junction-to-ambient thermal resistance |
104.5 |
°C/W |
RθJC(top) |
Junction-to-case(top) thermal resistance |
57.8 |
°C/W |
RθJB |
Junction-to-board thermal resistance |
46.8 |
°C/W |
ψJT |
Junction-to-top characterization parameter |
18.3 |
°C/W |
ψJB |
Junction-to-board characterization parameter |
46.4 |
°C/W |
RθJCbot |
Junction-to-case (bottom) thermal resistance |
N/A |
°C/W |
(1) For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics application report,
SPRA953.
6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 8 |
VCCO (1) – 0.5 |
|
|
V |
IOH = –20 μA; see Figure 8 |
VCCO – 0.1 |
|
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 8 |
|
|
0.4 |
V |
IOL = 20 μA; see Figure 8 |
|
|
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
480 |
|
mV |
IIH |
High-level input current |
VIH = VCCI(1) at INx or ENx |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
–10 |
|
|
CMTI |
Common-mode transient immunity |
VI = VCCI or 0 V; see Figure 11 |
25 |
70 |
|
kV/μs |
(1) VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.6 Supply Current Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
SUPPLY CURRENT |
MIN |
TYP |
MAX |
UNIT |
|
Supply current for VCC1 and VCC2 |
Disable |
EN1 = EN2 = 0 V |
ICC1, ICC2 |
|
0.8 |
1.6 |
mA |
DC to 1 Mbps |
DC signal: VI = VCCI or 0 V, AC signal: All channels switching with square wave clock input; CL = 15 pF |
ICC1 , ICC2 |
|
3.3 |
5 |
10 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
4.9 |
7 |
25 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
7.3 |
10 |
50 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
11.1 |
14.5 |
6.7 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 8 |
VCCO (1) – 0.5 |
|
|
V |
IOH = –20 μA; see Figure 8 |
VCCO – 0.1 |
|
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 8 |
|
|
0.4 |
V |
IOL = 20 μA; see Figure 8 |
|
|
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
460 |
|
mV |
IIH |
High-level input current |
VIH = VCCI(1) at INx or ENx |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
–10 |
|
|
CMTI |
Common-mode transient immunity |
VI = VCCI or 0 V; see Figure 11 |
25 |
50 |
|
kV/μs |
(1) VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.8 Supply Current Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
SUPPLY CURRENT |
MIN |
TYP |
MAX |
UNIT |
|
Supply current for VCC1 and VCC2 |
Disable |
EN1 = EN2 = 0 V |
ICC1, ICC2 |
|
0.5 |
1 |
mA |
DC to 1 Mbps |
DC signal: VI = VCCI or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
2.5 |
4 |
10 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
3.5 |
5 |
25 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
5 |
7 |
40 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
6.5 |
10 |
6.9 Electrical Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VOH |
High-level output voltage |
IOH = –2 mA; see Figure 8 |
VCCO (1) – 0.3 |
|
|
V |
IOH = –20 μA; see Figure 8 |
VCCO – 0.1 |
|
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 8 |
|
|
0.4 |
V |
IOL = 20 μA; see Figure 8 |
|
|
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
360 |
|
mV |
IIH |
High-level input current |
VIH = VCCI(1) at INx or ENx |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
–10 |
|
|
CMTI |
Common-mode transient immunity |
VI = VCCI or 0 V; see Figure 11 |
25 |
45 |
|
kV/μs |
(1) VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.10 Supply Current Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
SUPPLY CURRENT |
MIN |
TYP |
MAX |
UNIT |
|
Supply current for VCC1 and VCC2 |
Disable |
EN1 = EN2 = 0 V |
ICC1, ICC2 |
|
0.4 |
0.8 |
mA |
DC to 1 Mbps |
DC signal: VI = VCCI or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
2.2 |
3.5 |
10 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
3 |
4.2 |
25 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
4.2 |
5.5 |
40 Mbps |
All channels switching with square wave clock input; CL = 15 pF |
ICC1, ICC2 |
|
5.4 |
7.5 |
6.11 Power Dissipation Characteristics
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
PD |
Device power dissipation |
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF Input a 25-MHz, 50% duty cycle square wave |
|
|
170 |
mW |
6.12 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
tPLH, tPHL |
Propagation delay time |
See Figure 8 |
15 |
21 |
38 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 8 |
|
|
3.5 |
ns |
tsk(o) (2) |
Channel-to-channel output skew time |
Same-direction channels |
|
|
1.5 |
ns |
Opposite-direction channels |
|
|
6.5 |
tsk(pp) (3) |
Part-to-part skew time |
|
|
|
14 |
ns |
tr |
Output signal rise time |
See Figure 8 |
|
2.5 |
|
ns |
tf |
Output signal fall time |
See Figure 8 |
|
2.1 |
|
ns |
tPHZ, tPLZ |
Disable propagation delay, high/low-to-high impedance output |
See Figure 9 |
|
7 |
12 |
ns |
tPZH |
Enable propagation delay, high impedance-to-high output |
See Figure 9 |
|
6 |
12 |
ns |
tPZL |
Enable propagation delay, high impedance-to-low output |
See Figure 9 |
|
12 |
23 |
us |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 10 |
|
8 |
|
μs |
tGR |
Input glitch rejection time |
|
|
9.5 |
|
ns |
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads.
6.13 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
tPLH, tPHL |
Propagation delay time |
See Figure 8 |
16 |
25 |
46 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 8 |
|
|
3 |
ns |
tsk(o) (2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
2 |
ns |
Opposite-direction Channels |
|
|
6.5 |
tsk(pp) (3) |
Part-to-part skew time |
|
|
|
21 |
ns |
tr |
Output signal rise time |
See Figure 8 |
|
3 |
|
ns |
tf |
Output signal fall time |
See Figure 8 |
|
2.5 |
|
ns |
tPHZ, tPLZ |
Disable propagation delay, from high/low to high-impedance output |
See Figure 9 |
|
9 |
14 |
ns |
tPZH |
Enable propagation delay, from high-impedance to high output |
See Figure 9 |
|
9 |
17 |
ns |
tPZL |
Enable propagation delay, from high-impedance to low output |
See Figure 9 |
|
12 |
24 |
us |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 10 |
|
7 |
|
μs |
tGR |
Input glitch rejection time |
|
|
11 |
|
ns |
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
6.14 Switching Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
tPLH, tPHL |
Propagation delay time |
See Figure 8 |
18 |
28 |
50 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 8 |
|
|
3 |
ns |
tsk(o) (2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
3 |
ns |
Opposite-direction Channels |
|
|
8.5 |
ns |
tsk(pp) (3) |
Part-to-part skew time |
|
|
|
24 |
ns |
tr |
Output signal rise time |
See Figure 8 |
|
3.5 |
|
ns |
tf |
Output signal fall time |
See Figure 8 |
|
2.8 |
|
ns |
tPHZ, tPLZ |
Disable propagation delay, from high/low to high-impedance output |
See Figure 9 |
|
10 |
15 |
ns |
tPZH |
Enable propagation delay, from high-impedance to high output |
See Figure 9 |
|
10 |
19 |
ns |
tPZL |
Enable propagation delay, from high-impedance to low output |
See Figure 9 |
|
12 |
23 |
us |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 10 |
|
7 |
|
μs |
tGR |
Input glitch rejection time |
|
|
12 |
|
ns |
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads.
6.15 Typical Characteristics
Figure 1. ISO7142CC-Q1 Supply Current for All Channels vs Data Rate
Figure 2. High-Level Output Voltage
vs High-Level Output Current
Figure 3. Low-Level Output Voltage
vs Low-Level Output Current
Figure 5. Propagation Delay Time
vs Free-Air Temperature
Figure 7. Peak-Peak Output Jitter vs Data Rate
Figure 4. VCC Undervoltage Threshold
vs Free-Air Temperature
Figure 6. Input Glitch Rejection Time
vs Free-Air Temperature