The ISO7142CC-Q1 device provides galvanic isolation up to 2500 VRMS for 1 minute per UL 1577 and 4242-VPK per VDE V 0884-10. The
ISO7142CC-Q1 is a quad-channel isolator with two forward and two reverse-direction channels. This device is capable of maximum data rate of 50 Mbps with 5-V supplies and 40 Mbps with 3.3-V or 2.7-V supplies. The ISO7142CC-Q1 device has integrated filters on the inputs to support noise-prone applications.
Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, this device prevents noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. This device has TTL input thresholds and can operate from 2.7-V, 3.3-V, and 5-V supplies.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7142CC-Q1 | SSOP (16) | 4.90 mm × 3.90 mm |
DATE | REVISION | NOTES |
---|---|---|
December 2015 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN1 | 7 | I | Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low. |
EN2 | 10 | I | Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low. |
GND1 | 2 | — | Ground connection for VCC1 |
8 | |||
GND2 | 9 | — | Ground connection for VCC2 |
15 | |||
INA | 3 | I | Input, channel A |
INB | 4 | I | Input, channel B |
INC | 12 | I | Input, channel C |
IND | 11 | I | Input, channel D |
OUTA | 14 | O | Output, channel A |
OUTB | 13 | O | Output, channel B |
OUTC | 5 | O | Output, channel C |
OUTD | 6 | O | Output, channel D |
VCC1 | 1 | — | Power supply, VCC1 |
VCC2 | 16 | — | Power supply, VCC2 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Supply voltage(2) | VCC1, VCC2 | –0.5 | 6 | V | ||
Voltage | INx, OUTx, ENx | –0.5 | VCC + 0.5(3) | V | ||
IO | Output current | –15 | 15 | mA | ||
TJ | Maximum junction temperature | 150 | °C | |||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±4000 | V | |
Charged-device model (CDM), per AEC Q100-011 | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 2.7 | 5.5 | V | ||
IOH | High-level output current | VCC ≥ 3 V | –4 | mA | ||
VCC < 3 V | –2 | |||||
IOL | Low-level output current | 4 | mA | |||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
tui | Input pulse duration | VCC ≥ 4.5 V | 20 | ns | ||
VCC < 4.5 V | 25 | |||||
1 / tui | Signaling rate | VCC ≥ 4.5 V | 0 | 50 | Mbps | |
VCC < 4.5 V | 0 | 40 | ||||
TJ | Junction temperature | 136 | °C | |||
TA | Ambient temperature | –55 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO7142CC-Q1 | UNIT | ||
---|---|---|---|---|
DBQ (SSOP) | ||||
16 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 104.5 | °C/W | |
RθJC(top) | Junction-to-case(top) thermal resistance | 57.8 | °C/W | |
RθJB | Junction-to-board thermal resistance | 46.8 | °C/W | |
ψJT | Junction-to-top characterization parameter | 18.3 | °C/W | |
ψJB | Junction-to-board characterization parameter | 46.4 | °C/W | |
RθJCbot | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 8 | VCCO (1) – 0.5 | V | |||
IOH = –20 μA; see Figure 8 | VCCO – 0.1 | ||||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 8 | 0.4 | V | |||
IOL = 20 μA; see Figure 8 | 0.1 | ||||||
VI(HYS) | Input threshold voltage hysteresis | 480 | mV | ||||
IIH | High-level input current | VIH = VCCI(1) at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 11 | 25 | 70 | kV/μs |
PARAMETER | TEST CONDITIONS | SUPPLY CURRENT | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
Supply current for VCC1 and VCC2 | Disable | EN1 = EN2 = 0 V | ICC1, ICC2 | 0.8 | 1.6 | mA | ||
DC to 1 Mbps | DC signal: VI = VCCI or 0 V, AC signal: All channels switching with square wave clock input; CL = 15 pF |
ICC1 , ICC2 | 3.3 | 5 | ||||
10 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 4.9 | 7 | ||||
25 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 7.3 | 10 | ||||
50 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 11.1 | 14.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 8 | VCCO (1) – 0.5 | V | |||
IOH = –20 μA; see Figure 8 | VCCO – 0.1 | ||||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 8 | 0.4 | V | |||
IOL = 20 μA; see Figure 8 | 0.1 | ||||||
VI(HYS) | Input threshold voltage hysteresis | 460 | mV | ||||
IIH | High-level input current | VIH = VCCI(1) at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 11 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | SUPPLY CURRENT | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
Supply current for VCC1 and VCC2 | Disable | EN1 = EN2 = 0 V | ICC1, ICC2 | 0.5 | 1 | mA | ||
DC to 1 Mbps | DC signal: VI = VCCI or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF |
ICC1, ICC2 | 2.5 | 4 | ||||
10 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 3.5 | 5 | ||||
25 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 5 | 7 | ||||
40 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 6.5 | 10 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –2 mA; see Figure 8 | VCCO (1) – 0.3 | V | |||
IOH = –20 μA; see Figure 8 | VCCO – 0.1 | ||||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 8 | 0.4 | V | |||
IOL = 20 μA; see Figure 8 | 0.1 | ||||||
VI(HYS) | Input threshold voltage hysteresis | 360 | mV | ||||
IIH | High-level input current | VIH = VCCI(1) at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 11 | 25 | 45 | kV/μs |
PARAMETER | TEST CONDITIONS | SUPPLY CURRENT | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
Supply current for VCC1 and VCC2 | Disable | EN1 = EN2 = 0 V | ICC1, ICC2 | 0.4 | 0.8 | mA | ||
DC to 1 Mbps | DC signal: VI = VCCI or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF |
ICC1, ICC2 | 2.2 | 3.5 | ||||
10 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 3 | 4.2 | ||||
25 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 4.2 | 5.5 | ||||
40 Mbps | All channels switching with square wave clock input; CL = 15 pF | ICC1, ICC2 | 5.4 | 7.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PD | Device power dissipation | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF Input a 25-MHz, 50% duty cycle square wave |
170 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 8 | 15 | 21 | 38 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | See Figure 8 | 3.5 | ns | ||
tsk(o) (2) | Channel-to-channel output skew time | Same-direction channels | 1.5 | ns | ||
Opposite-direction channels | 6.5 | |||||
tsk(pp) (3) | Part-to-part skew time | 14 | ns | |||
tr | Output signal rise time | See Figure 8 | 2.5 | ns | ||
tf | Output signal fall time | See Figure 8 | 2.1 | ns | ||
tPHZ, tPLZ | Disable propagation delay, high/low-to-high impedance output | See Figure 9 | 7 | 12 | ns | |
tPZH | Enable propagation delay, high impedance-to-high output | See Figure 9 | 6 | 12 | ns | |
tPZL | Enable propagation delay, high impedance-to-low output | See Figure 9 | 12 | 23 | us | |
tfs | Fail-safe output delay time from input data or power loss | See Figure 10 | 8 | μs | ||
tGR | Input glitch rejection time | 9.5 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 8 | 16 | 25 | 46 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | See Figure 8 | 3 | ns | ||
tsk(o) (2) | Channel-to-channel output skew time | Same-direction Channels | 2 | ns | ||
Opposite-direction Channels | 6.5 | |||||
tsk(pp) (3) | Part-to-part skew time | 21 | ns | |||
tr | Output signal rise time | See Figure 8 | 3 | ns | ||
tf | Output signal fall time | See Figure 8 | 2.5 | ns | ||
tPHZ, tPLZ | Disable propagation delay, from high/low to high-impedance output | See Figure 9 | 9 | 14 | ns | |
tPZH | Enable propagation delay, from high-impedance to high output | See Figure 9 | 9 | 17 | ns | |
tPZL | Enable propagation delay, from high-impedance to low output | See Figure 9 | 12 | 24 | us | |
tfs | Fail-safe output delay time from input data or power loss | See Figure 10 | 7 | μs | ||
tGR | Input glitch rejection time | 11 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 8 | 18 | 28 | 50 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | See Figure 8 | 3 | ns | ||
tsk(o) (2) | Channel-to-channel output skew time | Same-direction Channels | 3 | ns | ||
Opposite-direction Channels | 8.5 | ns | ||||
tsk(pp) (3) | Part-to-part skew time | 24 | ns | |||
tr | Output signal rise time | See Figure 8 | 3.5 | ns | ||
tf | Output signal fall time | See Figure 8 | 2.8 | ns | ||
tPHZ, tPLZ | Disable propagation delay, from high/low to high-impedance output | See Figure 9 | 10 | 15 | ns | |
tPZH | Enable propagation delay, from high-impedance to high output | See Figure 9 | 10 | 19 | ns | |
tPZL | Enable propagation delay, from high-impedance to low output | See Figure 9 | 12 | 23 | us | |
tfs | Fail-safe output delay time from input data or power loss | See Figure 10 | 7 | μs | ||
tGR | Input glitch rejection time | 12 | ns |
TA = 25°C | CL = 15 pF |
TA = 25°C |
TA = 25°C |
TA = 25°C |
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
50 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | 0.014 | mm | |||
CI (2) | Input capacitance | VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V | 2 | pF | |||
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 | |||||||
VIOTM | Maximum transient isolation voltage | 4242 | VPK | ||||
VIORM | Maximum working isolation voltage | 566 | VPK | ||||
VPR | Input-to-output test voltage | After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC |
679 | VPK | |||
Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial discharge < 5 pC |
906 | ||||||
Method b1, 100% production test, VPR = VIORM x 1.875, t = 1 s, Partial discharge < 5 pC |
1061 | ||||||
L(I01) | Minimum air gap (clearance) | Shortest terminal to terminal distance through air | 3.7 | mm | |||
L(I02) | Minimum external tracking (creepage) | Shortest terminal to terminal distance across the package surface | 3.7 | mm | |||
Pollution degree | 2 | ||||||
CTI | Tracking resistance (comparative tracking index) | DIN EN 60112 (VDE 0303-11); IEC 60112 | ≥400 | V | |||
RIO (1) | Isolation resistance, input to output | VIO = 500 V, TA = 25oC | >1012 | Ω | |||
VIO = 500 V, 100oC ≤ TA ≤ 125oC | >1011 | ||||||
VIO = 500 V, TS = 150oC | >109 | ||||||
CIO (1) | Barrier capacitance, input to output | VI = 0.4 sin (2πft), f = 1 MHz | 2.4 | pF | |||
UL 1577 | |||||||
VISO | Withstanding Isolation voltage | VTEST = VISO= 2500 VRMS, 60 sec (qualification); VTEST = 1.2 * VISO= 3000 VRMS, 1 sec (100% production) |
2500 | VRMS |
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NOTE
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
PARAMETER | TEST CONDITIONS | SPECIFICATION |
---|---|---|
Material Group | II | |
Installation classification / Overvoltage Category for Basic Insulation | Rated mains voltage ≤ 150 VRMS | I–IV |
Rated mains voltage ≤ 300 VRMS | I–III |
VDE | UL | CSA | CQC |
---|---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 | Certified under UL 1577 Component Recognition Program | Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 | Plan to certify according to GB 4943.1-2011 |
Basic Insulation; Maximum transient Isolation IsolatiIsolationvoltage, 4242 VPK Maximum working isolation voltage, 566 VPK |
Single protection, 2500 VRMS (1) | 3000 VRMS Isolation rating; 185 VRMS Reinforced Insulation and 370 VRMS Basic Insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2; 150 VRMS Reinforced Insulation and 300 VRMS Basic Insulation per CSA 61010-1-12 and IEC 61010-1 3rd Ed. |
Basic Insulation, Altitude ≤ 5000m, Tropical climate, 250 VRMS maximum working voltage. |
File number: 40016131 | File number: E181974 | Master contract number: 220991 | Certification Planned |
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | DBQ-16 | θJA = 104.5°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | 217 | mA | ||
θJA = 104.5°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | 332 | ||||||
θJA = 104.5°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C | 443 | ||||||
TS | Maximum safety temperature | 150 | °C |
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
Table 2 lists the functional modes for the ISO7142CC-Q1.
VCCI | VCCO | INPUT (INx) |
OUTPUT ENABLE (ENx) |
OUTPUT (OUTx) |
---|---|---|---|---|
PU | PU | H | H or open | H |
L | H or open | L | ||
X | L | Z | ||
Open | H or open | H | ||
PD | PU | X | H or open | H |
PD | PU | X | L | Z |
X | PD | X | X | Undetermined |