SLLSEI6G September   2014  – January 2017 ISO7340C , ISO7340FC , ISO7341C , ISO7341FC , ISO7342C , ISO7342FC

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—5-V Supply
    10. 7.10 Supply Current Characteristics—5-V Supply
    11. 7.11 Electrical Characteristics—3.3-V Supply
    12. 7.12 Supply Current Characteristics—3.3-V Supply
    13. 7.13 Switching Characteristics—5-V Supply
    14. 7.14 Switching Characteristics—3.3-V Supply
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Isolated Data Acquisition System for Process Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Typical Supply Current Equations
            1. 10.2.1.2.1.1 ISO7340x
            2. 10.2.1.2.1.2 ISO7341x
            3. 10.2.1.2.1.3 ISO7342x
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application for Module With 16 Inputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Typical Application for RS-232 Interface
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC tst_cir_sllsei6.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Switching Characteristics Test Circuit and Voltage Waveforms
ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC delay_tim_sllsei6.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Enable/Disable Propagation Delay Time Test Circuit and Waveform
ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC failsafe_sllsei6.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC com_tran_imm_test_circ_sllsei6.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Common-Mode Transient Immunity Test Circuit