6 Specifications
6.1 Absolute Maximum Ratings
See (1)
|
MIN |
MAX |
UNIT |
VCC1
VCC2(2) |
Supply voltage |
–0.5 |
6 |
V |
|
Voltage |
INx, OUTx, ENx |
–0.5 |
6(3) |
V |
IO |
Output current |
|
±15 |
mA |
TJ |
Maximum junction temperature |
|
150 |
°C |
TSTG |
Storage temperature |
–65 |
150 |
°C |
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) |
±4000 |
V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) |
±1500 |
Machine model (MM), JEDEC JESD22-A115-A |
±200 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
|
MIN |
NOM |
MAX |
UNIT |
VCC1, VCC2 |
Supply voltage |
M-Grade |
2.7 |
|
5.5 |
V |
C-Grade |
3 |
|
5.5 |
IOH |
High-level output current |
–4 |
|
|
mA |
IOL |
Low-level output current |
|
|
4 |
mA |
VIH |
High-level input voltage |
2 |
|
5.5 |
V |
VIL |
Low-level input voltage |
0 |
|
0.8 |
V |
tui |
Input pulse duration |
M-Grade: ≥3-V Operation |
6.67 |
|
|
ns |
M-Grade: <3-V Operation |
10 |
|
|
C-Grade: ≥3-V Operation |
40 |
|
|
1 / tui |
Signaling rate |
M-Grade: ≥3-V Operation |
0 |
|
150 |
Mbps |
M-Grade: <3-V Operation |
0 |
|
100 |
C-Grade: ≥3-V Operation |
0 |
|
25 |
TJ |
Junction temperature |
–40 |
|
136 |
°C |
TA |
Ambient temperature |
–40 |
25 |
125 |
°C |
6.4 Thermal Information
THERMAL METRIC(1) |
ISO76x1Fx |
UNIT |
DW (SOIC) |
16 PINS |
RθJA |
Junction-to-ambient thermal resistance |
77.5 |
°C/W |
RθJC(top) |
Junction-to-case (top) thermal resistance |
40.4 |
°C/W |
RθJB |
Junction-to-board thermal resistance |
42.2 |
°C/W |
ψJT |
Junction-to-top characterization parameter |
15 |
°C/W |
ψJB |
Junction-to-board characterization parameter |
41.6 |
°C/W |
(1) For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics application report,
SPRA953.
6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10%
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 16 |
VCCO(1) – 0.8 |
4.8 |
|
VCCO – 0.8 |
4.7 |
|
V |
IOH = –20 μA; see Figure 16 |
VCCO – 0.1 |
5 |
|
VCCO – 0.1 |
5 |
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 16 |
|
0.2 |
0.4 |
|
0.3 |
0.5 |
V |
IOL = 20 μA; see Figure 16 |
|
0 |
0.1 |
|
0 |
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
450 |
|
|
450 |
|
mV |
IIH |
High-level input current |
VIH = VCC at INx or ENx |
|
|
10 |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
–10 |
|
|
-10 |
|
|
μA |
CMTI |
Common-mode transient immunity |
VI = VCCI (1) or 0 V; see Figure 19 |
25 |
75 |
|
25 |
75 |
|
kV/μs |
(1) V
CCI = Input-side supply voltage; V
CCO = Output-side supply voltage
6.6 Electrical Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10%
VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 16 |
OUTx on VCC1 (5 V) side |
VCC1 – 0.8 |
4.8 |
|
VCC1 – 0.8 |
4.7 |
|
V |
OUTx on VCC2 (3.3 V) side |
VCC2 - 0.4 |
3 |
|
VCC2 - 0.6 |
2.9 |
|
IOH = –20 μA; see Figure 16 |
OUTx on VCC1 (5 V) side |
VCC1 – 0.1 |
5 |
|
VCC1 – 0.1 |
5 |
|
OUTx on VCC2 (3.3 V) side |
VCC2 – 0.1 |
3.3 |
|
VCC2 – 0.1 |
3.3 |
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 16 |
|
0.2 |
0.4 |
|
0.3 |
0.5 |
V |
IOL = 20 μA; see Figure 16 |
|
0 |
0.1 |
|
0 |
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
430 |
|
|
430 |
|
mV |
IIH |
High-level input current |
VIH = VCC at INx or ENx |
|
|
10 |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
-10 |
|
|
-10 |
|
|
μA |
CMTI |
Common-mode transient immunity |
VI = VCCI (1) or 0 V; see Figure 19 |
25 |
50 |
|
25 |
50 |
|
kV/μs |
(1) VCCI = Input-side supply voltage
6.7 Electrical Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10%
VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 16 |
OUTx on VCC1 (3.3 V) side |
VCC1–0.4 |
3 |
|
VCC1-0.6 |
2.9 |
|
V |
OUTx on VCC2 (5 V) side |
VCC2–0.8 |
4.8 |
|
VCC2–0.8 |
4.7 |
|
IOH = –20 μA; see Figure 16 |
OUTx on VCC1 (3.3 V) side |
VCC1–0.1 |
3.3 |
|
VCC1–0.1 |
3.3 |
|
OUTx on VCC2 (5 V) side |
VCC2–0.1 |
5 |
|
VCC2–0.1 |
5 |
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 16 |
|
0.2 |
0.4 |
|
0.3 |
0.5 |
V |
IOL = 20 μA; see Figure 16 |
|
0 |
0.1 |
|
0 |
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
430 |
|
|
430 |
|
mV |
IIH |
High-level input current |
VIH = VCC at INx or ENx |
|
|
10 |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
-10 |
|
|
-10 |
|
|
μA |
CMTI |
Common-mode transient immunity |
VI = VCCI (1) or 0 V; see Figure 19 |
25 |
50 |
|
25 |
50 |
|
kV/μs |
(1) V
CCI = Input-side supply voltage
6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10%
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 16 |
VCCO(1) – 0.4 |
3 |
|
VCCO – 0.6 |
2.9 |
|
V |
IOH = –20 μA; see Figure 16 |
VCCO – 0.1 |
3.3 |
|
VCCO – 0.1 |
3.3 |
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 16 |
|
0.2 |
0.4 |
|
0.3 |
0.5 |
V |
IOL = 20 μA; see Figure 16 |
|
0 |
0.1 |
|
0 |
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
425 |
|
|
425 |
|
mV |
IIH |
High-level input current |
VIH = VCC at INx or ENx |
|
|
10 |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
-10 |
|
|
-10 |
|
|
μA |
CMTI |
Common-mode transient immunity |
VI = VCCI (1) or 0 V; see Figure 19 |
25 |
50 |
|
25 |
50 |
|
kV/μs |
(1) V
CCI = Input-side supply voltage; V
CCO = Output-side supply voltage
6.9 Electrical Characteristics: VCC1 and VCC2 at 2.7 V (ISO7631FM Only)
VCC1 and VCC2 at 2.7 V(1) (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VOH |
High-level output voltage |
IOH = –4 mA; see Figure 16 |
VCCO(2) – 0.5 |
2.4 |
|
V |
IOH = –20 μA; see Figure 16 |
VCCO – 0.1 |
2.7 |
|
VOL |
Low-level output voltage |
IOL = 4 mA; see Figure 16 |
|
0.2 |
0.4 |
V |
IOL = 20 μA; see Figure 16 |
|
0 |
0.1 |
VI(HYS) |
Input threshold voltage hysteresis |
|
|
350 |
|
mV |
IIH |
High-level input current |
VIH = VCC at INx or ENx |
|
|
10 |
μA |
IIL |
Low-level input current |
VIL = 0 V at INx or ENx |
-10 |
|
|
μA |
CMTI |
Common-mode transient immunity |
VI = VCCI (2) or 0 V; see Figure 19 |
25 |
50 |
|
kV/μs |
(1) Only M-Grade devices are recommended for operation down to 2.7 V supplies. For 2.7 V-operation, max data rate is 100 Mbps.
(2) VCCI = Input-side supply voltage; VCCO = Output-side supply voltage
6.10 Power Dissipation Characteristics
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
PD |
Maximum Device Power Dissipation |
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF Input a 75 MHz 50% duty cycle square wave |
|
|
399 |
mW |
6.11 Supply Current Characteristics: VCC1 and VCC2 at 5 V ± 10%
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
2.5 |
4 |
|
1.1 |
1.9 |
mA |
ICC2 |
|
3.7 |
5.4 |
|
1.5 |
2.6 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
2.6 |
4.1 |
|
1.8 |
2.7 |
mA |
ICC2 |
|
3.8 |
5.5 |
|
2.6 |
3.9 |
mA |
ICC1 |
10 Mbps |
|
3.3 |
4.5 |
|
2.7 |
3.7 |
mA |
ICC2 |
|
4.9 |
6.6 |
|
3.9 |
5.3 |
mA |
ICC1 |
25 Mbps |
|
4.5 |
6 |
|
4.1 |
5.4 |
mA |
ICC2 |
|
6.8 |
9 |
|
5.9 |
7.8 |
mA |
ICC1 |
150 Mbps |
|
15 |
19.5 |
Not Applicable |
mA |
ICC2 |
|
22 |
30 |
Not Applicable |
mA |
ISO7641F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
|
|
|
1.2 |
2.1 |
mA |
ICC2 |
|
|
|
|
1.6 |
2.6 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
|
|
|
1.8 |
2.8 |
mA |
ICC2 |
|
|
|
|
3.1 |
4.2 |
mA |
ICC1 |
10 Mbps |
|
|
|
|
3 |
4 |
mA |
ICC2 |
|
|
|
|
4.9 |
6.1 |
mA |
ICC1 |
25 Mbps |
|
|
|
|
4.8 |
6 |
mA |
ICC2 |
|
|
|
|
7.7 |
9.5 |
mA |
6.12 Supply Current Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10%
VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
2.5 |
4 |
|
1.1 |
1.9 |
mA |
ICC2 |
|
2.7 |
3.7 |
|
0.7 |
1.3 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
2.6 |
4.1 |
|
1.8 |
2.7 |
mA |
ICC2 |
|
2.8 |
3.8 |
|
1.8 |
2.6 |
mA |
ICC1 |
10 Mbps |
|
3.3 |
4.5 |
|
2.7 |
3.7 |
mA |
ICC2 |
|
3.5 |
4.6 |
|
2.6 |
3.5 |
mA |
ICC1 |
25 Mbps |
|
4.5 |
6 |
|
4.1 |
5.4 |
mA |
ICC2 |
|
4.7 |
5.9 |
|
3.8 |
5 |
mA |
ICC1 |
150 Mbps |
|
15 |
19.5 |
Not Applicable |
mA |
ICC2 |
|
14.6 |
19 |
Not Applicable |
mA |
ISO7641F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
|
|
|
1.2 |
2.1 |
mA |
ICC2 |
|
|
|
|
0.8 |
1.3 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
|
|
|
1.8 |
2.8 |
mA |
ICC2 |
|
|
|
|
2 |
2.9 |
mA |
ICC1 |
10 Mbps |
|
|
|
|
3 |
4 |
mA |
ICC2 |
|
|
|
|
3.2 |
4.1 |
mA |
ICC1 |
25 Mbps |
|
|
|
|
4.8 |
6 |
mA |
ICC2 |
|
|
|
|
5.1 |
7 |
mA |
6.13 Supply Current Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10%
VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
1.8 |
2.8 |
|
0.6 |
1.1 |
mA |
ICC2 |
|
3.7 |
5.4 |
|
1.5 |
2.6 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
1.9 |
2.9 |
|
1.2 |
1.8 |
mA |
ICC2 |
|
3.8 |
5.5 |
|
2.6 |
3.9 |
mA |
ICC1 |
10 Mbps |
|
2.4 |
3.4 |
|
1.8 |
2.6 |
mA |
ICC2 |
|
4.9 |
6.6 |
|
3.9 |
5.3 |
mA |
ICC1 |
25 Mbps |
|
3.2 |
4.2 |
|
2.7 |
3.6 |
mA |
ICC2 |
|
6.8 |
9 |
|
5.9 |
7.8 |
mA |
ICC1 |
150 Mbps |
|
9.3 |
12.5 |
Not Applicable |
mA |
ICC2 |
|
22 |
30 |
Not Applicable |
mA |
ISO7641F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
|
|
|
0.7 |
1.1 |
mA |
ICC2 |
|
|
|
|
1.6 |
2.6 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
|
|
|
1.2 |
1.9 |
mA |
ICC2 |
|
|
|
|
3.1 |
4.2 |
mA |
ICC1 |
10 Mbps |
|
|
|
|
2 |
2.8 |
mA |
ICC2 |
|
|
|
|
4.9 |
6.1 |
mA |
ICC1 |
25 Mbps |
|
|
|
|
3.1 |
4 |
mA |
ICC2 |
|
|
|
|
7.7 |
9.5 |
mA |
6.14 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V ± 10%
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
1.8 |
2.8 |
|
0.6 |
1.1 |
mA |
ICC2 |
|
2.7 |
3.7 |
|
0.7 |
1.3 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
1.9 |
2.9 |
|
1.2 |
1.8 |
mA |
ICC2 |
|
2.8 |
3.8 |
|
1.8 |
2.6 |
mA |
ICC1 |
10 Mbps |
|
2.4 |
3.4 |
|
1.8 |
2.6 |
mA |
ICC2 |
|
3.5 |
4.6 |
|
2.6 |
3.5 |
mA |
ICC1 |
25 Mbps |
|
3.2 |
4.2 |
|
2.7 |
3.6 |
mA |
ICC2 |
|
4.7 |
5.9 |
|
3.8 |
5 |
mA |
ICC1 |
150 Mbps |
|
9.3 |
12.5 |
Not Applicable |
mA |
ICC2 |
|
14.6 |
19 |
Not Applicable |
mA |
ISO7641F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
|
|
|
0.7 |
1.1 |
mA |
ICC2 |
|
|
|
|
0.8 |
1.3 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
|
|
|
1.2 |
1.9 |
mA |
ICC2 |
|
|
|
|
2 |
2.9 |
mA |
ICC1 |
10 Mbps |
|
|
|
|
2 |
2.8 |
mA |
ICC2 |
|
|
|
|
3.2 |
4.1 |
mA |
ICC1 |
25 Mbps |
|
|
|
|
3.1 |
4 |
mA |
ICC2 |
|
|
|
|
5.1 |
7 |
mA |
6.15 Supply Current Characteristics: VCC1 and VCC2 at 2.7 V (ISO7631FM Only) (1)
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
UNIT |
MIN |
TYP |
MAX |
ISO7631F |
ICC1 |
Disable |
EN1 = EN2 = 0 V |
|
1.5 |
2.4 |
mA |
ICC2 |
|
2.2 |
3.2 |
mA |
ICC1 |
DC to 1 Mbps |
DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF |
|
1.6 |
2.5 |
mA |
ICC2 |
|
2.3 |
3.2 |
mA |
ICC1 |
10 Mbps |
|
2 |
2.9 |
mA |
ICC2 |
|
3 |
3.9 |
mA |
ICC1 |
25 Mbps |
|
2.7 |
3.7 |
mA |
ICC2 |
|
3.9 |
4.9 |
mA |
ICC1 |
100 Mbps |
|
5.7 |
6.8 |
mA |
ICC2 |
|
8.6 |
12 |
mA |
6.16 Switching Characteristics: VCC1 and VCC2 at 5 V ± 10%
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F, ISO7641F |
tPLH, tPHL |
Propagation delay time |
See Figure 16 |
3.5 |
7 |
10.5 |
11 |
17 |
28 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 16 |
|
|
2 |
|
|
3 |
ns |
tsk(o)(2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
2 |
|
|
3 |
ns |
Opposite-direction Channels |
|
|
3 |
|
|
4 |
tsk(pp)(3) |
Part-to-part skew time |
|
|
|
4.5 |
|
|
13 |
ns |
tr |
Output signal rise time |
See Figure 16 |
|
1.6 |
|
|
2.8 |
|
ns |
tf |
Output signal fall time |
See Figure 16 |
|
1 |
|
|
2.9 |
|
ns |
tPHZ |
Disable Propagation Delay, high-to-high impedance output |
See Figure 17 |
|
5 |
16 |
|
8 |
20 |
ns |
tPLZ |
Disable Propagation Delay, low-to-high impedance output |
See Figure 17 |
|
5 |
16 |
|
7 |
20 |
ns |
tPZH |
Enable Propagation Delay, high impedance-to-high output |
See Figure 17 |
|
4 |
16 |
|
11000 |
22000(4) |
ns |
tPZL |
Enable Propagation Delay, high impedance-to-low output |
See Figure 17 |
|
4 |
16 |
|
8 |
20 |
ns |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 18 |
|
9.5 |
|
|
9 |
|
μs |
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate for C-grade devices should be ≤ 45 Kbps.
6.17 Switching Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10%
VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F, ISO7641F |
tPLH, tPHL |
Propagation delay time |
See Figure 16 |
4 |
8 |
13 |
11 |
18 |
32 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 16 |
|
|
2 |
|
|
3.5 |
ns |
tsk(o)(2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
2.5 |
|
|
4.5 |
ns |
Opposite-direction Channels |
|
|
3.5 |
|
|
5.5 |
tsk(pp)(3) |
Part-to-part skew time |
|
|
|
6 |
|
|
15 |
ns |
tr |
Output signal rise time |
See Figure 16 |
|
2 |
|
|
3.6 |
|
ns |
tf |
Output signal fall time |
See Figure 16 |
|
1.2 |
|
|
3.3 |
|
ns |
tPHZ |
Disable Propagation Delay, high-to-high impedance output |
See Figure 17 |
|
6.5 |
17 |
|
9 |
20 |
ns |
tPLZ |
Disable Propagation Delay, low-to-high impedance output |
See Figure 17 |
|
6.5 |
17 |
|
8 |
20 |
ns |
tPZH |
Enable Propagation Delay, high impedance-to-high output |
See Figure 17 |
|
5.5 |
17 |
|
11000 |
22000(4) |
ns |
tPZL |
Enable Propagation Delay, high impedance-to-low output |
See Figure 17 |
|
5.5 |
17 |
|
10 |
30 |
ns |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 18 |
|
9.5 |
|
|
8.5 |
|
μs |
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate for C-grade devices should be ≤ 45 Kbps.
6.18 Switching Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10%
VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F, ISO7641F |
tPLH, tPHL |
Propagation delay time |
See Figure 16 |
4 |
7.5 |
12.5 |
11 |
18.5 |
32 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 16 |
|
|
2 |
|
|
2.5 |
ns |
tsk(o)(2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
2.5 |
|
|
4.5 |
ns |
Opposite-direction Channels |
|
|
3.5 |
|
|
5.5 |
tsk(pp)(3) |
Part-to-part skew time |
|
|
|
6 |
|
|
15 |
ns |
tr |
Output signal rise time |
See Figure 16 |
|
1.7 |
|
|
2.9 |
|
ns |
tf |
Output signal fall time |
See Figure 16 |
|
1.1 |
|
|
2.9 |
|
ns |
tPHZ |
Disable Propagation Delay, high-to-high impedance output |
See Figure 17 |
|
5.5 |
17 |
|
8 |
20 |
ns |
tPLZ |
Disable Propagation Delay, low-to-high impedance output |
See Figure 17 |
|
5.5 |
17 |
|
7 |
20 |
ns |
tPZH |
Enable Propagation Delay, high impedance-to-high output |
See Figure 17 |
|
4.5 |
17 |
|
11000 |
22000(4) |
ns |
tPZL |
Enable Propagation Delay, high impedance-to-low output |
See Figure 17 |
|
4.5 |
17 |
|
8 |
30 |
ns |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 18 |
|
9.5 |
|
|
7.5 |
|
μs |
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate for C-grade devices should be ≤ 45 Kbps.
6.19 Switching Characteristics: VCC1 and VCC2 at 3.3 V ± 10%
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
C-Grade |
UNIT |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
ISO7631F, ISO7641F |
tPLH, tPHL |
Propagation delay time |
See Figure 16 |
4 |
8.5 |
14 |
12 |
23 |
35 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 16 |
|
|
2 |
|
|
3 |
ns |
tsk(o)(2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
3 |
|
|
5 |
ns |
Opposite-direction Channels |
|
|
4 |
|
|
6 |
tsk(pp)(3) |
Part-to-part skew time |
|
|
|
6.5 |
|
|
16 |
ns |
tr |
Output signal rise time |
See Figure 16 |
|
2 |
|
|
3.7 |
|
ns |
tf |
Output signal fall time |
See Figure 16 |
|
1.3 |
|
|
3.4 |
|
ns |
tPHZ |
Disable Propagation Delay, high-to-high impedance output |
See Figure 17 |
|
6.5 |
17 |
|
9 |
20 |
ns |
tPLZ |
Disable Propagation Delay, low-to-high impedance output |
See Figure 17 |
|
6.5 |
17 |
|
8 |
20 |
ns |
tPZH |
Enable Propagation Delay, high impedance-to-high output |
See Figure 17 |
|
5.5 |
17 |
|
11000 |
22000(4) |
ns |
tPZL |
Enable Propagation Delay, high impedance-to-low output |
See Figure 17 |
|
5.5 |
17 |
|
10 |
30 |
ns |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 18 |
|
9.2 |
|
|
7.5 |
|
μs |
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate for C-grade devices should be ≤ 45 Kbps.
6.20 Switching Characteristics: VCC1 and VCC2 at 2.7 V (2)
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
M-Grade |
|
MIN |
TYP |
MAX |
UNIT |
ISO7631F, ISO7641F |
tPLH, tPHL |
Propagation delay time |
See Figure 16 |
5 |
8 |
16 |
ns |
PWD(1) |
Pulse width distortion |tPHL – tPLH| |
See Figure 16 |
|
|
2.5 |
ns |
tsk(o)(2) |
Channel-to-channel output skew time |
Same-direction Channels |
|
|
4 |
ns |
Opposite-direction Channels |
|
|
5 |
tsk(pp)(3) |
Part-to-part skew time |
|
|
|
8 |
ns |
tr |
Output signal rise time |
See Figure 16 |
|
2.3 |
|
ns |
tf |
Output signal fall time |
See Figure 16 |
|
1.8 |
|
ns |
tPHZ |
Disable Propagation Delay, high-to-high impedance output |
See Figure 17 |
|
8 |
18 |
ns |
tPLZ |
Disable Propagation Delay, low-to-high impedance output |
See Figure 17 |
|
8 |
18 |
ns |
tPZH |
Enable Propagation Delay, high impedance-to-high output |
See Figure 17 |
|
7 |
18 |
ns |
tPZL |
Enable Propagation Delay, high impedance-to-low output |
See Figure 17 |
|
7 |
18 |
ns |
tfs |
Fail-safe output delay time from input data or power loss |
See Figure 18 |
|
8.5 |
|
μs |
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
6.21 Typical Characteristics
Figure 1. ISO7631FM Supply Current Per Channel
vs Data Rate
Figure 3. ISO7631FC Supply Current Per Channel
vs Data Rate
Figure 5. ISO7641FC Supply Current Per Channel
vs Data Rate
Figure 7. M-Grade High-Level Output Voltage
vs High-Level Output Current
Figure 9. C-Grade High-Level Output Voltage
vs High-Level Output Current
Figure 11. VCC Undervoltage Threshold
vs Free Air Temperature
Figure 13. C-Grade Propagation Delay Time
vs Free Air Temperature
Figure 15. C-Grade Output Jitter vs Data Rate
Figure 2. ISO7631FM Supply Current For All Channels
vs Data Rate
Figure 4. ISO7631FC Supply Current For All Channels
vs Data Rate
Figure 6. ISO7641FC Supply Current For All Channels
vs Data Rate
Figure 8. M-Grade Low-Level Output Voltage
vs Low-Level Output Current
Figure 10. C-Grade Low-Level Output Voltage
vs Low-Level Output Current
Figure 12. M-Grade Propagation Delay Time
vs Free Air Temperature
Figure 14. M-Grade Output Jitter vs Data Rate