SLLSEM2H November   2014  – November 2024 ISO7821

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Dissipation Characteristics
    6. 5.6  Electrical Characteristics, 5 V
    7. 5.7  Electrical Characteristics, 3.3 V
    8. 5.8  Electrical Characteristics, 2.5 V
    9. 5.9  Power Ratings
    10. 5.10 Insulation Specifications
    11. 5.11 Safety-Related Certifications
    12. 5.12 Safety Limiting Values
    13. 5.13 Switching Characteristics, 5 V
    14. 5.14 Switching Characteristics, 3.3 V
    15. 5.15 Switching Characteristics, 2.5 V
    16. 5.16 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 8.2.3 Application Performance Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 PCB Material
      2. 8.4.2 Layout Guidelines
      3. 8.4.3 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWW|16
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Insulation Specifications

Table 5-2 Insulation Characteristics
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
DW DWW
DTI Distance through the insulation Minimum internal gap (internal clearance) 21 21 μm
VIOWM Maximum working isolation voltage Time dependent dielectric breakdown (TDDB) test 1500 2000 VRMS
2121 2828 VDC
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIOTM Maximum transient isolation voltage VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)		 8000 8000 VPK
VIOSM Maximum surge isolation voltage Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK(1) (qualification)		 8000 8000 VPK
VIORM Maximum repetitive peak isolation voltage 2121 2828 VPK
VPR Input-to-output test voltage Method a, After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC		 2545 3394 VPK
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial Discharge < 5 pC		 3394 4525
Method b1,After environmental tests subgroup 1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC		 3977 5303
RS Isolation resistance VIO = 500 V at TS >109 >109 Ω
Pollution degree 2 2
Climatic category 55/125/21 55/125/21
UL 1577
VISO Withstanding isolation voltage VTEST = VISO = 5700 VRMS, t = 60 sec (qualification);
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100% production)		 5700 5700 VRMS
(1) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Table 5-3 Package Insulation and Safety-Related Specifications (over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLR External clearance Shortest terminal-to-terminal distance through air DW-16 8.15 mm
DWW-16 14.5 15.0
CPG External creepage Shortest terminal-to-terminal distance across the package surface DW-16 8.15 mm
DWW-16 14.5 15.0
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A 600 V
RIO Isolation resistance, input to output(1) VIO = 500 V, TA = 25°C 1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ max 1011 Ω
CIO Barrier capacitance, input to output(1) VIO = 0.4 x sin (2πft), f = 1 MHz 1 pF
CI Input capacitance(2) VI = VCC/2 + 0.4 x sin (2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
Note:

Creepage and clearance requirements must be applied according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to verify that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.