SLLSEM2F November   2014  – March 2016 ISO7821

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Dissipation Characteristics
    6. 6.6  Electrical Characteristics, 5 V
    7. 6.7  Electrical Characteristics, 3.3 V
    8. 6.8  Electrical Characteristics, 2.5 V
    9. 6.9  Switching Characteristics, 5 V
    10. 6.10 Switching Characteristics, 3.3 V
    11. 6.11 Switching Characteristics, 2.5 V
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Voltage Feature Description
        1. 8.3.1.1 Regulatory Information
        2. 8.3.1.2 Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Performance Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 PCB Material
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWW|16
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage(2) VCC1, VCC2 –0.5 6 V
Voltage INx, OUTx –0.5 VCC + 0.5(3) V
Output Current IO -15 15 mA
Surge Immunity 12.8 kV
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC1, VCC2 Supply voltage 2.25 5.5 V
IOH High-level output current VCCO(2) = 5 V -4 mA
VCCO = 3.3 V -2
VCCO = 2.5 V -1
IOL Low-level output current VCCO = 5 V 4 mA
VCCO = 3.3 V 2
VCCO = 2.5 V 1
VIH High-level input voltage 0.7 x VCCI(2) VCCI V
VIL Low-level input voltage 0 0.3 x VCCI V
DR Signaling rate 0 100 Mbps
TJ Junction temperature(1) -55 150 °C
TA Ambient temperature -55 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
(2) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.4 Thermal Information

THERMAL METRIC(1) ISO7821 UNIT
DW (SOIC) DWW (SOIC)
16 PINS 16-PINS
RθJA Junction-to-ambient thermal resistance 84.7 84.7 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 47.3 46.0 °C/W
RθJB Junction-to-board thermal resistance 49.4 54.5 °C/W
ψJT Junction-to-top characterization parameter 19.1 18.5 °C/W
ψJB Junction-to-board characterization parameter 48.8 53.8 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance n/a n/a °C/W
(1) For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Dissipation Characteristics

VALUE UNIT
PD Maximum power dissipation by ISO7821x VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, input a 50 MHz 50% duty cycle square wave		 100 mW
PD1 Maximum power dissipation by side-1 of ISO7821x 50
PD2 Maximum power dissipation by side-2 of ISO7821x 50

6.6 Electrical Characteristics, 5 V

VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 7 VCCO(1) – 0.4 VCCO – 0.2 V
VOL Low-level output voltage IOL = 4 mA; see Figure 7 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 x VCCO(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10
CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 10 100 kV/μs
Supply Current - ISO7821DW and ISO7821FDW
ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 1.2 1.7 mA
ICC1, ICC2 DC Signal VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.4 mA
ICC1, ICC2 1 Mbps All channels switching with square wave clock input;
CL = 15 pF		 1.8 2.6 mA
ICC1, ICC2 10 Mbps 2.4 3.2 mA
ICC1, ICC2 100 Mbps 7.5 9.3 mA
Supply Current - ISO7821DWW and ISO7821FDWW
ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 0.7 1.1 mA
ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 1.8 2.9 mA
ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 1.2 1.7 mA
ICC1, ICC2 DC Signal VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.5 mA
ICC1, ICC2 1 Mbps All channels switching with square wave clock input; CL = 15 pF 1.9 2.7 mA
ICC1, ICC2 10 Mbps 2.5 3.2 mA
ICC1, ICC2 100 Mbps 7.7 9.3 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.7 Electrical Characteristics, 3.3 V

VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 7 VCCO(1) – 0.4 VCCO – 0.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 7 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 x VCCO V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10
CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 10 100 kV/μs
Supply Current - ISO7821DW and ISO7821FDW
ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 1.2 1.7 mA
ICC1, ICC2 DC Signal VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.4 mA
ICC1, ICC2 1 Mbps All channels switching with square wave clock input; CL = 15 pF 1.8 2.6 mA
ICC1, ICC2 10 Mbps 2.2 3 mA
ICC1, ICC2 100 Mbps 5.8 7.1 mA
Supply Current - ISO7821DWW and ISO7821FDWW
ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 0.7 1.1 mA
ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 1.8 2.9 mA
ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 1.2 1.7 mA
ICC1, ICC2 DC Signal VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.5 mA
ICC1, ICC2 1 Mbps All channels switching with square wave clock input; CL = 15 pF 1.9 2.6 mA
ICC1, ICC2 10 Mbps 2.3 3 mA
ICC1, ICC2 100 Mbps 5.9 7.1 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.8 Electrical Characteristics, 2.5 V

VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 7 VCCO(1) – 0.4 VCCO – 0.2 V
VOL Low-level output voltage IOL = 1 mA; see Figure 7 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 x VCCO V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10
CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 10 100 kV/μs
Supply Current - ISO7821DW and ISO7821FDW
ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 1.2 1.7 mA
ICC1, ICC2 DC Signal VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.4 mA
ICC1, ICC2 1 Mbps All channels switching with square wave clock input; CL = 15 pF 1.8 2.6 mA
ICC1, ICC2 10 Mbps 2.1 2.8 mA
ICC1, ICC2 100 Mbps 4.9 5.9 mA
Supply Current - ISO7821DWW and ISO7821FDWW
ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 0.7 1.1 mA
ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 1.8 2.9 mA
ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI(1)(ISO7821) 1.2 1.7 mA
ICC1, ICC2 DC Signal VI = VCCI(1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.5 mA
ICC1, ICC2 1 Mbps All channels switching with square wave clock input; CL = 15 pF 1.9 2.6 mA
ICC1, ICC2 10 Mbps 2.2 2.9 mA
ICC1, ICC2 100 Mbps 5 6 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.9 Switching Characteristics, 5 V

VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7 6 10.7 16 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 0.6 4.6
tsk(pp) (2) Part-to-part skew time 4.5 ns
tr Output signal rise time See Figure 7 2.4 3.9 ns
tf Output signal fall time 2.4 3.9
tPHZ Disable propagation delay, high-to-high impedance output for ISO7821DWW and ISO7821FDWW See Figure 8 12 20 ns
tPLZ Disable propagation delay, low-to-high impedance output for ISO7821DWW and ISO7821FDWW 12 20 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7821DWW 10 20 ns
Enable propagation delay, high impedance-to-high output for ISO7821FDWW 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7821DWW 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7821FDWW 10 20 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 0.2 9 μs
tie Time interval error 216 - 1 PRBS data at 100 Mbps 1 ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics, 3.3 V

VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7 6 10.8 16 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 0.7 4.7
tsk(pp) (2) Part-to-part skew time 4.5 ns
tr Output signal rise time See Figure 7 1.3 3
tf Output signal fall time 1.3 3
tPHZ Disable propagation delay, high-to-high impedance output for ISO7821DWW and ISO7821FDWW See Figure 8 17 32 ns
tPLZ Disable propagation delay, low-to-high impedance output for ISO7821DWW and ISO7821FDWW 17 32 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7821DWW 17 32 ns
Enable propagation delay, high impedance-to-high output for ISO7821FDWW 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7821DWW 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7821FDWW 17 32 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 0.2 9 μs
tie Time interval error 216 - 1 PRBS data at 100 Mbps 1 ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.11 Switching Characteristics, 2.5 V

VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7 7.5 11.7 17.5 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 0.7 4.7
tsk(pp) (2) Part-to-part skew time 4.5 ns
tr Output signal rise time See Figure 7 1.8 3.5
tf Output signal fall time 1.8 3.5
tPHZ Disable propagation delay, high-to-high impedance output for ISO7821DWW and ISO7821FDWW See Figure 8 22 45 ns
tPLZ Disable propagation delay, low-to-high impedance output for ISO7821DWW and ISO7821FDWW 22 45 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7821DWW 18 45 ns
Enable propagation delay, high impedance-to-high output for ISO7821FDWW 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7821DWW 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7821FDWW 18 45 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 0.2 9 μs
tie Time interval error 216 - 1 PRBS data at 100 Mbps 1 ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.12 Typical Characteristics

ISO7821 ISO7821F D001_SLLSEM2.gif
TA = 25°C CL = 15 pF
Figure 1. Supply Current vs Data Rate (with 15 pF Load)
ISO7821 ISO7821F D003_SLLSEM2.gif
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output Current
ISO7821 ISO7821F D005_SLLSEM2.gif
Figure 5. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7821 ISO7821F D002_SLLSEM2.gif
TA = 25°C CL = No Load
Figure 2. Supply Current vs Data Rate (with No Load)
ISO7821 ISO7821F D004_SLLSEM2.gif
TA = 25°C
Figure 4. Low-Level Output Voltage vs Low-Level Output Current
ISO7821 ISO7821F D006_SLLSEP0.gif
A.
Figure 6. Propagation Delay Time vs Free-Air Temperature