Two layers are sufficient to accomplish a
low EMI PCB design.
- Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
- For best performance, it is recommended to minimize the length of D+/D- board
traces from the MCU to ISOUSB111, and from ISOUSB111 to the connector. Vias and
stubs on D+/D- lines must be avoided.
- Placing a solid ground plane just below the
high-speed signal layer establishes controlled impedance for transmission line
interconnects and provides an excellent low-inductance path for the return
current flow. D+ and D- traces must be designed for 90-Ω differential impedance
and as close to 45-Ω single ended impedance as possible.
- Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2.
- Decoupling capacitors must be placed on the top layer, and the routing between
the capacitors and the corresponding to supply and ground pins must be completed
in the top layer itself. There should not be any vias in the routing path
between the decoupling capacitors and the corresponding supply and ground
pins.
- ESD structures must be placed on the top layer, close to the connector, and
right on the D+/D- traces without vias. Ground routing for the ESD structures
must be made in the top layer if possible, else must have a strong connection to
the ground plane with multiple vias.
- Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.