SLLSFC6D November   2021  – January 2023 ISOUSB111

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply Options
      2. 8.3.2 Power Up
      3. 8.3.3 Symmetric Operation, Dual-Role Port and Role-Reversal
      4. 8.3.4 Connect and Speed Detection
      5. 8.3.5 Disconnect Detection
      6. 8.3.6 Reset
      7. 8.3.7 LS/FS Message Traffic
      8. 8.3.8 L2 Power Management State (Suspend) and Resume
      9. 8.3.9 L1 Power Management State (Sleep) and Resume
    4. 8.4 Device Functional Modes
  9. 9 Power Supply Recommendations
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Isolated Host or Hub
      2. 10.1.2 Isolated Peripheral - Self-Powered
      3. 10.1.3 Isolated Peripheral - Bus-Powered
      4. 10.1.4 Application Curve
        1. 10.1.4.1 Insulation Lifetime
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 PCB Material
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Electrical Characteristics

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CHARACTERISTICS
IVBUSx or IV3P3Vx VBUS or V3P3V current consumption - Full Speed (FS) and Low Speed (LS) modes Receive side FS Active (6 MHz signal rate), Figure 7-9, CL = 50 pF 12 15.3 mA
Transmit side FS Active (6 MHz signal rate), Figure 7-9, CL = 50 pF 9.5 13 mA
Receive side LS Active (750 kHz signal rate), Figure 7-10, CL = 450 pF 11 13.5 mA
Transmit side LS Active (750 kHz signal rate), Figure 7-10, CL = 450 pF 9.5 13 mA
FS/LS Idle State (US side or DS side) 7.4 11 mA
IVBUSx or IV3P3Vx VBUS or V3P3V current consumption - L1 Sleep mode Upstream Facing side 7.5 9.8 mA
Downstream Facing side 7.3 9.5 mA
IVBUSx or IV3P3Vx VBUS or V3P3V current consumption - L2 Suspend mode Upstream Facing side 1.07 1.55 mA
Downstream Facing side 5.6 7.5 mA
IVBUSx or IV3P3Vx VBUS or V3P3V current consumption - Not attached Upstream Facing side 6.2 8.5 mA
Downstream Facing side 6.2 8.9 mA
UV+(VBUSx) (1) Under voltage threshold when supply voltage is rising, VBUS 4.0 V
UV-(VBUSx) (1) Under voltage threshold when supply voltage is falling, VBUS 3.6 V
UVHYS(VBUSx) (1) Under voltage threshold hysteresis, VBUS 0.08 V
UV+(V3P3Vx) Under voltage threshold when supply voltage is rising, V3P3V  2.95 V
UV-(V3P3Vx) Under voltage threshold when supply voltage is falling, V3P3V  1.95 V
UVHYS(V3P3Vx) Under voltage threshold hysteresis, V3P3V  0.11 V
DIGITAL INPUTS
VIH High-level input voltage 0.7 x V3PV3x V
VIL Low-level input voltage 0.3 x V3PV3x V
VIHYS Input transition threshold hysteresis 0.3 V
IIH High-level input current 1 µA
IIL Low-level input current 10 µA
DIGITAL OUTPUTS (V1OK, V2OK)
VOH High-level output voltage IO = -3 mA for 3.0 V ≤ V3P3Vx ≤ 3.6 V V3P3Vx - 0.2 V
VOL Low-level output voltage IO = 3 mA for 3.0 V ≤ V3P3Vx ≤ 3.6 V 0.2 V
UDx, DDx, INPUT CAPACITANCE AND TERMINATION
ZINP_xDx Impedance to GND, no pull up/down Vin=3.6 V, V3P3Vx=3.0 V, TJ < 125 ℃, USB 2.0 Spec Section 7.1.6 300 kΩ
CIO_xDx Capacitance to GND Measured with VNA at 240MHz, Driver Hi-Z 10 pF
RPUI Bus Pull up Resistor on Upstream Facing Port (idle) USB 2.0 Spec Section 7.1.5 0.9 1.1 1.575 kΩ
RPUR Bus Pull up Resistor on Upstream Facing Port (receiving) USB 2.0 Spec Section 7.1.5 1.5 2.2 3 kΩ
RPD Bus Pull-down Resistor on Downstream Facing Port USB 2.0 Spec Section 7.1.5 14.25 19 24.8 kΩ
VTERM Termination voltage for Upstream facing port pullup (RPU) USB 2.0 Spec Section 7.1.5, measured on D+ or D- with pull up enabled on upstream port with external load disconnected. 3 3.6 V
UDx, DDx, INPUT LEVELS LS/FS
VIH High (driven) USB 2.0 Spec Section 7.1.4 (measured at connector) 2 V
VIHZ High (floating) USB 2.0 Spec Section 7.1.4 (Host downstream port pull down resistor enabled and Device pulled up to 3.0 V - 3.6 V). 2.7 3.6 V
VIL Low USB 2.0 Spec Section 7.1.4 0.8 V
VDI Differential Input Sensitivity |(xD+)-(xD-)|; USB 2.0 Spec Figure 7-19; (measured at connector) 0.2 V
VCM Common Mode Range Includes VDI range; USB 2.0 Spec Figure 7-19; (measured at connector) 0.8 2.5 V
UDx, DDx, OUTPUT LEVELS LS/FS
VOL Low USB 2.0 Spec Section 7.1.1, (measured at connector with RL of 0.9 kΩ to 3.6 V. ) 0 0.3 V
VOH High (Driven) USB 2.0 Spec Section 7.1.1 (measured at connector with RL of 14.25 kΩ to GND. ) 2.8 3.6 V
VOSE1 SE1 USB 2.0 Spec Section 7.1.1 0.8 V
ZFSTERM Driver Series Output Resistance USB 2.0 Spec Section 7.1.1 and Figure 7-4, Measured during VOL or VOH 28 44 Ω
VCRS Output Signal Crossover Voltage Measured as in USB 2.0 Spec Section 7.1.1 Figures 7-8, 7-9 and 7-10; Excluding the first transition from the Idle state 1.3 2 V
THERMAL SHUTDOWN
TSD+ Thermal shutdown turn-on temperature 160 170 180 °C
TSD- Thermal shutdown turn-off temperature 150 160 170 °C
TSDHYS Thermal shutdown hysteresis 10 °C
(1) If VBUSx pins are externally connected to the corresponding V3P3Vx  pins, then UVLO thresholds on VBUSx are governed by  UV+(V3P3Vx) , UV-(V3P3Vx) and UVHYS(V3P3Vx)