SLLSF40B November 2017 – September 2019 ISOW7821
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VISO | Isolated supply voltage | External IISO = 0 to 50 mA | 4.75 | 5.07 | 5.43 | V |
External IISO = 0 to 130 mA | 4.5 | 5.07 | 5.43 | |||
VISO(LINE) | DC line regulation | IISO = 50 mA, VCC = 4.5 V to 5.5 V | 2 | mV/V | ||
VISO(LOAD) | DC load regulation | IISO = 0 to 130 mA | 1% | |||
EFF | Efficiency at maximum load current | IISO = 130 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7821); VI =0 V (ISOW7821 with F suffix) |
53% | |||
VCC+(UVLO) | Positive-going UVLO threshold on VCC, VISO | 2.7 | V | |||
VCC–(UVLO) | Negative-going UVLO threshold on VCC, VISO | 2.1 | V | |||
VHYS (UVLO) | UVLO threshold hysteresis on VCC, VISO | 0.2 | V | |||
VITH | Input pin rising threshold | 0.7 | VSI | |||
VITL | Input pin falling threshold | 0.3 | VSI | |||
VI(HYS) | Input pin threshold hysteresis (INx) | 0.1 | VSI | |||
IIL | Low level input current | VIL = 0 at INx or SEL | –10 | µA | ||
IIH | High level input current | VIH = VSI(1) at INx or SEL | 10 | µA | ||
VOH | High level output voltage | IO = –4 mA, see Figure 24 | VSO(1) – 0.4 | VSO – 0.2 | V | |
VOL | Low level output voltage | IO = 4 mA, see Figure 24 | 0.2 | 0.4 | V | |
|CMH| | High-level common-mode transient immunity | VI = VSI, VCM = 1000 V; see Figure 25 | 100 | kV/µs | ||
|CML| | Low-level common-mode transient immunity | VI = 0 V, VCM = 1000 V; see Figure 25 | 100 | kV/µs | ||
ICC_SC | DC current from supply under short circuit on VISO | VISO shorted to GND2 | 137 | mA | ||
VISO(RIP) | Output ripple on isolated supply (pk-pk) | 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF, IISO = 130 mA | 100 | mV |