SLLSEY2G March 2017 – August 2021 ISOW7840 , ISOW7841 , ISOW7842 , ISOW7843 , ISOW7844
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VISO | Isolated supply voltage | External IISO = 0 to 30 mA | 3.13 | 3.34 | 3.58 | V |
External IISO = 0 to 75 mA | 3 | 3.34 | 3.58 | |||
VISO(LINE) | DC line regulation | IISO = 30 mA, VCC = 3 V to 3.6 V | 2 | mV/V | ||
VISO(LOAD) | DC load regulation | IISO = 0 to 75 mA | 1% | |||
EFF | Efficiency at maximum load current | IISO = 75 mA, CLOAD = 0.1 µF || 10 µF; VI = VSI (ISOW784x); VI = 0 V (ISOW784x with F suffix) | 47% | |||
VCC+(UVLO) | Positive-going UVLO threshold on VCC, VISO | 2.7 | V | |||
VCC–(UVLO) | Negative-going UVLO threshold on VCC, VISO | 2.1 | V | |||
VHYS (UVLO) | UVLO threshold hysteresis on VCC, VISO | 0.2 | V | |||
VITH | Input pin rising threshold | 0.7 | VSI | |||
VITL | Input pin falling threshold | 0.3 | VSI | |||
VI(HYS) | Input pin threshold hysteresis (INx) | 0.1 | VSI | |||
IIL | Low level input current | VIL = 0 at INx or SEL | –10 | µA | ||
IIH | High level input current | VIH = VSI(1) at INx or SEL | 10 | µA | ||
VOH | High level output voltage | IO = –2 mA, see Figure 8-1 | VSO(1) – 0.3 | VSO – 0.1 | V | |
VOL | Low level output voltage | IO = 2 mA, see Figure 8-1 | 0.1 | 0.3 | V | |
CMTI | Common mode transient immunity | VI = VSI or 0 V, VCM = 1000 V; see Figure 8-2 | 100 | kV/us | ||
ICC_SC | DC current from supply under short circuit on VISO | VISO shorted to GND2 | 143 | mA | ||
VISO(RIP) | Output ripple on isolated supply (pk-pk) | 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF, IISO = 75 mA | 90 | mV |