SLPS732B june   2021  – april 2023 JFE150

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultra-Low Noise
      2. 8.3.2 Low Gate Current
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Capacitive Transducer Input Stage
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The JFE150 is a Burr-Brown™ discrete JFET built using Texas Instruments' modern, high-performance, analog bipolar process. The JFE150 features performance not previously available in older discrete JFET technologies. The JFE150 offers the maximum possible noise-to-power efficiency and flexibility, where the quiescent current can be set by the user and yields excellent noise performance for currents from 50 μA to 20 mA. When biased at 5 mA, the device yields 0.8 nV/√Hz of input-referred noise, giving ultra-low noise performance with extremely high input impedance (> 1 TΩ). The JFE150 also features integrated diodes connected to separate clamp nodes to provide protection without the addition of high-leakage, nonlinear, external diodes.

The JFE150 can withstand a high drain-to-source voltage of 40 V, as well as gate-to-source and gate-to-drain voltages down to –40 V. The temperature range is specified from –40°C to +125°C. The device is offered in 5-pin SOT-23 and SC70 packages.

Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
JFE150 DBV (SOT-23, 5) 2.90 mm × 1.60 mm
DCK (SC70, 5) 2.00 mm × 1.25 mm
(1) For all available packages, see the package option addendum at the end of the data sheet.
Device Summary
PARAMETER VALUE
VGSS Gate-to-source breakdown voltage –40 V
VDSS Drain-to-source breakdown voltage ±40 V
CISS Input capacitance 24 pF
TJ Junction temperature –40°C to +125°C
IDSS Drain-to-source saturation current 35 mA

 

GUID-20210429-CA0I-QKGS-JW8F-X2MKFMBXLCWX-low.svgFunctional Block Diagram
GUID-20210618-CA0I-C55B-MQP0-VCFS9KMSNJXR-low.pngUltra-Low Input Voltage Noise