SLPS732B june   2021  – april 2023 JFE150

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultra-Low Noise
      2. 8.3.2 Low Gate Current
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Capacitive Transducer Input Stage
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 5 V (unless otherwise noted)

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Figure 6-1 Drain-to-Source Current vs Gate-to-Source Voltage
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Figure 6-3 Drain-to-Source Current vs Drain-to-Source Voltage
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Figure 6-5 Gate Current vs Drain-to-Source Voltage
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VDS = 5 V
Figure 6-7 Gate-to-Source Voltage vs Temperature
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Figure 6-9 Input-Referred Noise Density vs Frequency
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f = 1 kHz
Figure 6-11 Input-Referred Noise Spectral Density vs Drain‑to‑Source Current
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Figure 6-2 Drain-to-Source Current vs Drain-to-Source Voltage
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Figure 6-4 Common Source Transconductance vs Drain-to-Source Current
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Figure 6-6 Gate Current vs Gate-to-Source Voltage
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Figure 6-8 IDSS vs Drain-to-Source Voltage
GUID-20210616-CA0I-NZVX-PRLG-KDLBTKZF17KC-low.png
f = 1 kHz
Figure 6-10 Noise Density Contributors vs Input Gate Resistance
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Figure 6-12 Input, Output, and Reverse Transfer Capacitance vs Drain-to-Source Voltage