SLPS732B june   2021  – april 2023 JFE150

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultra-Low Noise
      2. 8.3.2 Low Gate Current
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Capacitive Transducer Input Stage
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, IDS = 2 mA, and VDS = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE
en Input-referred voltage noise density IDS = 100 µA , VDS = 5 V f = 10 Hz 3 nV/√Hz
f = 1 kHz 2
IDS = 2 mA, VDS = 5 V f = 10 Hz 1.6
f = 1 kHz 0.9
IDS = 5 mA, VDS = 5 V f = 10 Hz 1.8
f = 1 kHz 0.8
Input-referred voltage noise f = 0.1 Hz to 10 Hz,
VDS = 5 V		 IDS = 100 µA 0.19 µVPP
IDS = 2 mA 0.09
IDS = 5 mA 0.13
ei Input current noise f = 1 kHz, VDS = 5 V 1.8 fA/√Hz
INPUT CURRENT
IG Input gate current VDS = 2 V, VGS = –0.7 V, VVCH = 5 V,  VVCL = –5 V 0.2 ±10 pA
VDS = 0 V, VGS = –30 V 0.2
TA = –40°C to +85°C ±2000
TA = –40°C to +125°C ±10000
INPUT VOLTAGE
VGSS Gate-to-source breakdown voltage VDS = 0 V, |IG| < 100 µA −40 V
VGSC Gate-to-source cutoff voltage VDS = 10 V, IDS = 0.1 µA −1.5 −1.2 −0.9 V
VGS Gate-to-source voltage IDS = 100 µA –1.3 –0.7 V
IDS = 2 mA –1.1 –0.5
INPUT IMPEDANCE
RIN Gate input resistance VGS = –5 V to 0 V,  VDS = 0 V 1 TΩ
CISS Input capacitance VDS = 0 V 30 pF
VDS = 5 V 24
CRSS Reverse transfer capacitance VDS = 0 V 7
OUTPUT
IDSS Drain-to-source saturation current VDS = 10 V,  VGS = 0 V  24 35 46 mA
TA = –40°C to +125°C 22 57
gm Transconductance  IDS = 100 µA 3 mS
IDS = 2 mA 18
GFS Full conduction transconductance VDS = 10 V,  VGS = 0 V 55 68 80 mS
VDSS Drain-to-source breakdown voltage |IDS| < 100 µA, VGS = –2 V 40 V
COSS Output capacitance VDS = 5 V 8 pF