SLPS730B august   2021  – august 2023 JFE2140

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precision Matching
      2. 8.3.2 Ultra-Low Noise
      3. 8.3.3 Low Gate Current
      4. 8.3.4 Input Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Cascode Configuration
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Front-End Design
        1. 9.2.2.1 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.4 Composite Amplifiers

The JFE2140 can be configured to provide a low-noise, high-input impedance front-end stage for a typical op amp. Open-loop transistor gain stages shown previously suffer from wide gain variations that are dependent on the forward transcondutance of the JFE2140. When precision gain is required, the composite amplifier (JFET front-end + operational amplifier) achieves excellent results by allowing for a fixed gain determined by external resistors, and improving the noise and bandwidth of the operational amplifier. The JFE2140 gain stage provides a boost to the open-loop performance of the system, extending the bandwidth beyond what the operational amplifier alone can provide, and gives a high-input impedance, ultra-low noise input stage to interface with high source impedance microphones.

Figure 9-7 shows a generic schematic representation of a voltage-feedback composite amplifier. The component requirements and tradeoffs are listed in Table 9-1.

GUID-20210810-SS0I-4LPG-7XFL-B4FZM9L4PVKK-low.gif Figure 9-6 Low Noise, High Input Impedance Composite Amplifier

The gain of Figure 9-7 can be calculated using the following equation:

Equation 2. A= 1+RF1RF2
Table 9-1 Composite Amplifier Component List and Function
COMPONENT DESCRIPTION
RS1 Degeneration resistors. These resistors reduce the overall gain of the JFET stage, but improve the linearity performance. Also, when used in differential configurations (see OPA1637 reference design), the resistors reduce CMRR errors that occur as a result of input mismatch voltages.
RS2 Bias-current setting resistor. This resistor, along with RS1, determine the bias current when using resistive biasing (see Figure 9-4). Be aware that both RS1 and RS2 resistance directly impact noise performance.
RG Gate resistor. This resistor is used to help limit current flow into the gate in overvoltage cases. For improved dc precision, match RG to the equivalent parallel resistance of RS1 || RS2. Use the low resistance values to minimize the thermal noise impact on the circuit.
RD Drain resistor. This resistor sets the JFET stage gain in common source biasing, along with gm and RS1 + RS2. Higher resistance increases gain, but lowers the nominal VDS voltage.
RF1 Feedback resistor 1. Along with RF2, this resistor sets the gain of the composite amplifier.
RF2 Feedback resistor 2. Along with RF1, this resistor sets the gain of the composite amplifier.
RS2 Source resistor 2. Along with RS1, this resistor sets the dc bias current where the JFET is nominally operated.
CS Source capacitor. This capacitor reduces the noise coupling from RS2.