The VDD and VIO pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. The typical recommended bypass capacitance is a 0.1-µF ceramic X5R or X7R dielectric capacitor. Some applications may require additional supply bypassing for optimal LDC1001 operation. For these applications, the smallest-valued capacitor should be placed closest to the corresponding supply pin.
The optimum placement is closest to the VDD/VIO and GND/DGND pins of the device. Take care to minimize the loop area formed by the bypass capacitor connection, the VDD/VIO pin, and the GND/DGND pin of the IC. See Figure 21 for a PCB layout example.
The CLDO pin should be bypassed to digital ground (DGND) with a 56-nF ceramic bypass capacitor.
Connect the filter capacitor selected for the application using the procedure described in Choosing Filter Capacitor (CFA and CFB Pins) between the two CFA and CFB pins. Place the filter capacitor close to the CFA and CFB pins. Do not use any ground or power plane below the capacitor and the trace connecting the capacitor and the CFA /CFB pins.
Use separate ground planes for the GND and DGND with a star connection. See Figure 21 for a PCB layout example.
The sensor capacitor should be a C0G capacitor placed as close as possible to the sensor coil.