SNOSD15B December   2016  – April 2017 LDC2112 , LDC2114

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Digital Interface
    7. 6.7 I2C Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Multi-Channel and Single-Channel Operation
      2. 7.3.2 Button Output Interfaces
      3. 7.3.3 Programmable Button Sensitivity
      4. 7.3.4 Baseline Tracking
      5. 7.3.5 Integrated Button Algorithms
      6. 7.3.6 I2C Interface
        1. 7.3.6.1 Selectable I2C Address (LDC2112 Only)
        2. 7.3.6.2 I2C Interface Specifications
        3. 7.3.6.3 I2C Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Power Mode
      2. 7.4.2 Low Power Mode
      3. 7.4.3 Configuration Mode
    5. 7.5 Register Maps
      1. 7.5.1 Individual Register Listings
        1. 7.5.1.1 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Theory of Operation
      2. 8.1.2  Designing Sensor Parameters
      3. 8.1.3  Setting COM Pin Capacitor
      4. 8.1.4  Defining Power-On Timing
      5. 8.1.5  Configuring Button Scan Rate
      6. 8.1.6  Programming Button Sampling Window
      7. 8.1.7  Scaling Frequency Counter Output
      8. 8.1.8  Setting Button Triggering Threshold
      9. 8.1.9  Tracking Baseline
      10. 8.1.10 Mitigating False Button Detections
        1. 8.1.10.1 Eliminating Common-Mode Change (Anti-Common)
        2. 8.1.10.2 Resolving Simultaneous Button Presses (Max-Win)
        3. 8.1.10.3 Overcoming Case Twisting (Anti-Twist)
        4. 8.1.10.4 Mitigating Metal Deformation (Anti-Deform)
      11. 8.1.11 Reporting Interrupts for Button Presses and Error Conditions
      12. 8.1.12 Estimating Supply Current
    2. 8.2 Typical Application
      1. 8.2.1 Touch Button Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 DSBGA Light Sensitivity
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Export Control Notice
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The COM pin must be bypassed to ground with an appropriate value capacitor. For details of how to choose the capacitor value, refer to Setting COM Pin Capacitor. CCOM should be placed as close as possible to the COM pin. The COM signal should be tied to a small copper fill placed underneath the INn signals. The INn signals should stay clear of other high frequency traces.

Each active channel needs to have an LC resonator connected to the corresponding INn pins. The sensor capacitor should be placed within 10 mm of the corresponding INn pin, and the inductor (NOT shown in Figure 32) should be placed at the appropriate location next to (but not touching) the metal target. The INn traces should be at least 6 mil (0.15 mm) wide to minimize parasitic inductances.

For the DSBGA package, the inner four device pads (INTB, OUT3, LPWRB, and SDA) should be routed out on an inner layer through vias, with the traces offset to reduce coupling with other signals. These four vias may need to use blind vias or microvias to bring the signals out. The PCB layer stack should use a thinner (4 mil or 0.1 mm thickness) dielectric between the top copper and next copper layer so that microvias can be used.

10.2 Layout Example

LDC2112 LDC2114 ldc2114-layout-with-decoupling-capacitors-and-sensor-capacitors-snosd15.png Figure 32. Layout of LDC2114 (DSBGA-16) With Decoupling Capacitors and Sensor Capacitors
LDC2112 LDC2114 ldc2114-pcb-layout-snosd15.png Figure 33. Layout of LDC2114 (TSSOP-16) With Decoupling Capacitors and Sensor Capacitors

10.3 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect.