SNOSD47C december   2018  – july 2023 LDC5072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Diagnostics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Supply Voltage
      2. 8.3.2 Excitation Signal
      3. 8.3.3 Signal Processing Block
        1. 8.3.3.1 Demodulation
        2. 8.3.3.2 Fixed Gain Control
        3. 8.3.3.3 Automatic Gain Control
      4. 8.3.4 Output Stage
      5. 8.3.5 Diagnostics
        1. 8.3.5.1 Undervoltage Diagnostics
        2. 8.3.5.2 Initialization Diagnostics
        3. 8.3.5.3 Normal State Diagnostics
        4. 8.3.5.4 Fault State Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 IDLE State
      2. 8.4.2 DIAGNOSTICS State
      3. 8.4.3 NORMAL State
      4. 8.4.4 FAULT State
      5. 8.4.5 DISABLED State
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 5-V Supply Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VREG and VCC
          2. 9.2.1.2.2 Output Capacitors
          3. 9.2.1.2.3 AGC Mode
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3.3-V Supply Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VREG and VCC
          2. 9.2.2.2.2 Output Capacitors
          3. 9.2.2.2.3 Fixed Gain Mode
      3. 9.2.3 Redundancy Mode
      4. 9.2.4 Single-Ended Mode
      5. 9.2.5 External Diagnostics Required for Loss of VCC or GND
  11. 10Power Supply Recommendations
    1. 10.1 Mode 1: VCC = 5 V, VREG = 3.3 V
    2. 10.2 Mode 2: VCC = VREG = 3.3 V
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 Output Stage

The output stage consists of buffers that drive each of the outputs differentially and maintain the output common mode at VREF_OUT as specified in SpecificationsSpecifications. There are two output stages, one at the OUT0x pins and the other at the OUT1x pins, and each drive the pins in a push-pull manner. For a rotating input, one set of pins will represent the sine angle information and other set will represent cosine angle information. The output stages buffer the AGC output and outputs the final demodulated position information to be used by a microcontroller. The output stage is designed such that it can drive a large range of capacitive loads.

The output stage requires external capacitors as specified by COUT and pullup or pulldown resistors as specified by RPD_OUT and RPU_OUT. The OUTx pins enter a high impedance state in the case of a fault, so the pullup and pulldown resistors are used to pull the voltage out of range for detection by the MCU. See External Diagnostics Required for Loss of VCC or GND for details about external diagnostics required for loss of VCC or GND conditions.

There is a possibility that wires connecting to OUT0 and OUT1 pins can be routed outside the sensor module, so the output stage has both negative and high voltage protection to prevent the part from getting damaged in the event of shorts. The output stage also has out-of-range fault detection. The diagnostic coverage on output stage will also check if the output signal is being driven outside of the maximum allowable limit as defined in SpecificationsSpecifications as shown in Figure 8-4. In the event of a fault, the output stages are put in Hi-Z mode and external pullup and pulldown resistors will drive OUTx pins to maximum and minimum signaling a fault to the microcontroller. See DiagnosticsDiagnosticsDiagnosticsDiagnosticsDiagnosticsDiagnostics for details.

GUID-E998BA12-F867-4D2A-9525-C20543A8AF09-low.gifFigure 8-4 Out of Operation Fault Detection Range at the Output
Note:

The voltage at the OUTx pins is not ratiometric to VCC. In AGC mode, the calculated RADIUS in Equation 8 value will change. Only if it crosses one of the threshold (depending on change magnitude of VCC), then the gain of AGC will be adjusted accordingly to bring the RADIUS value back to AGC_TARGET. In fixed-gain mode, the gain will not be adjusted even if VCC change by large magnitude.