SNVS609K December   2008  – June 2022 LM25088 , LM25088-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM25088
    3. 6.3 ESD Ratings: LM25088-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Low-Dropout Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  Oscillator and Sync Capability
      4. 7.3.4  Error Amplifier and PWM Comparator
      5. 7.3.5  Ramp Generator
      6. 7.3.6  Dropout Voltage Reduction
      7. 7.3.7  Frequency Dithering (LM25088-1 Only)
      8. 7.3.8  Cycle-by-Cycle Current Limit
      9. 7.3.9  Overload Protection Timer (LM25088-2 Only)
      10. 7.3.10 Soft Start
      11. 7.3.11 HG Output
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN Pin Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor
        2. 8.2.2.2  Output Inductor
        3. 8.2.2.3  Current Sense Resistor
        4. 8.2.2.4  Ramp Capacitor
        5. 8.2.2.5  Output Capacitors
        6. 8.2.2.6  Input Capacitors
        7. 8.2.2.7  VCC Capacitor
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 Output Voltage Divider
        11. 8.2.2.11 UVLO Divider
        12. 8.2.2.12 Restart Capacitor (LM5008-2 Only)
        13. 8.2.2.13 MOSFET Selection
        14. 8.2.2.14 Diode Selection
        15. 8.2.2.15 Snubber Components Selection
        16. 8.2.2.16 Error Amplifier Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

MOSFET Selection

Selection of the buck MOSFET is governed by the same trade-offs as the switching frequency. Losses in power MOSFETs can be broken down into conduction losses and switching losses. The conduction loss is given by:

Equation 23. PDC = D × (IO2 × RDS(ON) × 1.3)

where

  • D is the duty cycle.
  • IO is the maximum load current.

The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, for a more precise calculation, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using the RDS(ON) vs. Temperature curves in the MOSFET data sheet.

The switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition period, both current and voltage are present in the MOSFET. The switching loss can be approximated as:

Equation 24. PSW = 0.5 × VIN × IO × (tR + tF) × fSW

where

  • tR and tF are the rise and fall times of the MOSFET.

The rise and fall times are usually mentioned in the MOSFET data sheet or can be empirically observed on the scope. Another loss, which is associated with the buck MOSFET, is the “gate-charging loss.” This loss differs from the above two losses in the sense that it is dissipated in the LM25088 and not in the MOSFET itself. Gate charging loss, PGC, results from the drive current charging the gate capacitance of the power MOSFET and is approximated as:

Equation 25. PGC = VCC × Qg × fSW

For this example with the maximum input voltage of 36 V, the VDS breakdown rating of the selected MOSFET must be greater than 36 V, plus any ringing across drain to source due to parasitics. To minimize switching time and gate drive losses, the selected MOSFET must also have low gate charge (Qg). A good choice of MOSFET for this design example is the SI7848DP, which has a total gate charge of 30 nC and rise and fall times of 10 ns and 12 ns, respectively.