SNVS609K December   2008  – June 2022 LM25088 , LM25088-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM25088
    3. 6.3 ESD Ratings: LM25088-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Low-Dropout Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  Oscillator and Sync Capability
      4. 7.3.4  Error Amplifier and PWM Comparator
      5. 7.3.5  Ramp Generator
      6. 7.3.6  Dropout Voltage Reduction
      7. 7.3.7  Frequency Dithering (LM25088-1 Only)
      8. 7.3.8  Cycle-by-Cycle Current Limit
      9. 7.3.9  Overload Protection Timer (LM25088-2 Only)
      10. 7.3.10 Soft Start
      11. 7.3.11 HG Output
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN Pin Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor
        2. 8.2.2.2  Output Inductor
        3. 8.2.2.3  Current Sense Resistor
        4. 8.2.2.4  Ramp Capacitor
        5. 8.2.2.5  Output Capacitors
        6. 8.2.2.6  Input Capacitors
        7. 8.2.2.7  VCC Capacitor
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 Output Voltage Divider
        11. 8.2.2.11 UVLO Divider
        12. 8.2.2.12 Restart Capacitor (LM5008-2 Only)
        13. 8.2.2.13 MOSFET Selection
        14. 8.2.2.14 Diode Selection
        15. 8.2.2.15 Snubber Components Selection
        16. 8.2.2.16 Error Amplifier Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

PARAMETER(3)(4)TEST CONDITIONSTJ = –40°C to +125°CTJ = 25°CUNIT
MINTYPMAXMINTYP(2)MAX
VIN SUPPLY
IBIASVIN operating currentVFB = 1.3 V4.53.2mA
ISTANDBYVIN standby currentVEN = 1 V3.02.5mA
ISHUTDOWNVIN shutdown currentVEN = 0 V2414µA
VCC REGULATOR
VVCC(Reg)VCC regulationVVCC = open7.48.27.8V
VVCC(Reg)VCC regulationVVIN = 4.5 V, VVCC = open4.34.5V
VCC sourcing current limitVVCC = 02530mA
VVCC(UV)VCC undervoltage lockout thresholdPositive going VVCC3.74.24V
VCC undervoltage hysteresis200mV
ENABLE THRESHOLDS
EN shutdown thresholdVEN rising320480400mV
EN shutdown hysteresisVEN falling100mV
EN standby thresholdVEN rising1.11.31.2V
EN standby hysteresisVEN falling120mV
EN pullup current sourceVEN = 0 V5µA
SOFT START
SS pullup current SourceVSS = 0 V81311µA
FB to SS offsetVFB = 1.3 V150mV
ERROR AMPLIFIER
VREFFB reference voltageMeasured at FB pin
FB = COMP		1.1871.2231.205V
FB input bias currentVFB = 1.2 V10018nA
COMP sink and source current3mA
AOLDC gain60dB
FBWUnity gain bandwidth3MHz
PWM COMPARATORS
THG(OFF)Forced HG off time185365280ns
TON(MIN)Minimum HG on timeVVIN = 36 V55ns
COMP to PWM comparator offset930mV
OSCILLATOR (RT Pin)
LM25088-2 (non-dithering)
fnom1Nominal oscillator frequencyRRT = 31.6 kΩ180220200kHz
fnom2 Nominal oscillator frequencyRRT = 11.3 kΩ430565500kHz
LM25088-1 (dithering)
fminDithering rangeMinimum dither frequencyfnom – 5%kHz
fmax Dithering rangeMaximum dither frequencyfnom + 5%kHz
SYNC
SYNC positive threshold2.3V
SYNC pulse width15150ns
CURRENT LIMIT
VCS(TH)Cycle-by-cycle sense voltage thresholdVRAMP = 0 V112136120mV
Cycle-by-cycle current limit delayVRAMP = 2.5 V280ns
Buck switch VDS protectionVIN to SW1.5V
CURRENT LIMIT RESTART (RES PIN)
VresupRES threshold upper (rising)VCS = 0.1251.11.31.2V
VresdownRES threshold lower (falling)0.10.30.2V
IchargeCharge source currentVCS ≥ 0.125406550µA
IdischargeDischarge sink currentVCS < 0.125203427µA
IrampdownDischarge sink current (post fault)0.81.61.2µA
RAMP GENERATOR
IRAMP1RAMP current 1(1)VVIN = 36 V, VOUT = 10 V135195165µA
IRAMP2RAMP current 2(1)VVIN = 10 V, VOUT = 10 V183025µA
VOUT bias currentVOUT = 24 V125µA
RAMP output low voltage(1)VVIN = 36 V, VOUT = 10 V200mV
HIGH SIDE (HG) GATE DRIVER
VOLHHG low-state output voltageIHG = 100 mA215115mV
VOHHHG High-state output voltageIHG = –100 mA, VOHH = VBOOT – VHG240mV
HG rise timeCload = 1000 pF12ns
HG fall timeCload = 1000 pF6ns
IOHHPeak HG Source CurrentVHG = 0V1.5A
IOLHPeak HG sink currentVHG = VVCC2A
BOOT UVLOBOOT to SW3V
Pre RDS(ON)Pre-charge switch ON-resistanceIVCC = 1 mA72Ω
Pre-charge switch on time300ns
THERMAL
TSDThermal shutdown temperatureJunction temperature rising165°C
Thermal shutdown hysteresisJunction temperature falling25°C
(1) RAMP and COMP are output pins. As such they are not specified to have an external voltage applied.
(2) Typical specifications represent the most likely parametric norm at 25°C operation.
(3) Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent at TJ = 25°C, and are provided for reference purposes only.
(4) Unless otherwise stated the following conditions apply: VVIN = 24 V, VVCC= 8 V, VEN = 5 V, RRT = 31.6 kΩ. No load on HG.