Connection between L1 and SW pin should be kept as short as possible to minimize inductance
Connection between CCUK and SW should also be kept short
The feedback resistor should be placed close to the NFB pin to minimize the path of the higher impedance feedback node
The feedback trace leading from Vout to the output to the feedback resistors should not pass under the switch node between L1 and CCUK and the switch node between CCUK, L2 and D
The feedback trace leading from Vout to the output to the feedback resistors should not pass under the inductors L1 and L2
A bypass capacitor CBYP of 0.1 µF should be placed close to VIN and GND pin