SNVS561G September   2008  – September 2015 LM3150

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Ratings
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programming the Output Voltage
      2. 8.3.2 Regulation Comparator
      3. 8.3.3 Overvoltage Comparator
      4. 8.3.4 Current Limit
      5. 8.3.5 Short-Circuit Protection
      6. 8.3.6 Soft-Start
      7. 8.3.7 Thermal Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH Tools
        2. 9.2.2.2 LM3150 Design Procedure
        3. 9.2.2.3 Design Guide
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Custom Design with WEBENCH Tools
      2. 12.1.2 Receiving Notification of Documentation Updates
      3. 12.1.3 Third-Party Products Disclaimer
      4. 12.1.4 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

HTSSOP PWP
14 PINS
Top View
LM3150 LM3150_Buck_Controller_pinout.gif

Pin Functions

PIN I/O DESCRIPTION FUNCTION
NAME NO.
VCC 1 O Supply Voltage for FET Drivers Nominally regulated to 5.95 V. Connect a 1.0-µF to 4.7-µF decoupling capacitor from this pin to ground.
VIN 2 I Input Supply Voltage Supply pin to the device. Nominal input range is 6 V to 42 V.
EN 3 I Enable To enable the IC, apply a logic high signal to this pin greater than 1.26-V typical or leave floating. To disable the part, ground the EN pin.
FB 4 I Feedback Internally connected to the regulation, overvoltage, and short-circuit comparators. The regulation setting is 0.6 V at this pin. Connect to feedback resistor divider between the output and ground to set the output voltage.
SGND 5,9 — Signal Ground Ground for all internal bias and reference circuitry. Should be connected to PGND at a single point.
SS 6 I Soft-Start An internal 7.7-µA current source charges an external capacitor to provide the soft-start function.
RON 7 I On-time Control An external resistor from VIN to this pin sets the high-side switch on-time.
ILIM 8 I Current Limit Monitors current through the low-side switch and triggers current limit operation if the inductor valley current exceeds a user defined value that is set by RLIM and the Sense current, ILIM-TH, sourced out of this pin during operation.
SW 10 O Switch Node Switch pin of controller and high-gate driver lower supply rail. A boost capacitor is also connected between this pin and BST pin
HG 11 O High-Side Gate Drive Gate drive signal to the high-side NMOS switch. The high-side gate driver voltage is supplied by the differential voltage between the BST pin and SW pin.
BST 12 I Connection for Bootstrap Capacitor High-gate driver upper supply rail. Connect a 0.33 to 0.47-µF capacitor from SW pin to this pin. An internal diode charges the capacitor during the high-side switch off-time. Do not connect to an external supply rail.
LG 13 O Low-Side Gate Drive Gate drive signal to the low-side NMOS switch. The low-side gate driver voltage is supplied by VCC.
PGND 14 G Power Ground Synchronous rectifier MOSFET source connection. Tie to power ground plane. Should be tied to SGND at a single point.
EP — — Exposed Pad Exposed die attach pad should be connected directly to SGND. Also used to help dissipate heat out of the IC.