7.3.1 Control Overview

The LM34926 regulator employs a control principle based on a comparator and a one-shot on-timer, with the output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the reference the internal buck switch is switched on for the one-shot timer period, which is a function of the input voltage and the programming resistor (RT). Following the on-time the switch remains off until the FB voltage falls below the reference, and the forced minimum off-time has expired. When the FB pin voltage falls below the reference and the off-time one-shot period expires, the buck switch is then turned on for another on-time one-shot period. This continues until regulation is achieved and the FB voltage is approximately equal to 1.225 V (typical).

In a synchronous buck converter, the low-side (sync) FET is on when the high-side (buck) FET is off. The inductor current ramps up when the high-side switch is on and ramps down when the high-side switch is off. There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of the output loading. The operating frequency remains relatively constant with load and line variations. The operating frequency can be determined from Equation 1.

Equation 1.

where

The output voltage (V_OUT) is set by two external resistors (R_FB1, R_FB2). The regulated output voltage is determined from Equation 2.

Equation 2.

This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum amount of ESR for the output capacitor (C_OUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is required for the LM34926 device. In cases where the capacitor ESR is too small, additional series resistance may be required (R_C in Figure 9).

For applications where lower output voltage ripple is required the output can be taken directly from a low ESR output capacitor, as shown in Figure 9. However, R_C slightly degrades the load regulation.

Figure 9. Low Ripple Output Configuration

7.3.2 V_CC Regulator

The LM34926 device contains an internal high-voltage linear regulator with a nominal output of 7.6 V. The input pin (V_IN) can be connected directly to the line voltages up to 100 V. The V_CC regulator is internally current limited to 30 mA. The regulator sources current into the external capacitor at V_CC. This regulator supplies current to internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the V_CC pin reaches the UVLO threshold of 4.5 V, the IC is enabled.

The V_CC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive boot capacitor when the SW pin is low.

At high input voltages, the power dissipated in the high-voltage regulator is significant and can limit the overall achievable output power. As an example, with the input at 48 V and switching at high frequency, the V_CC regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the V_CC voltage is driven externally by an alternate voltage source, from 8.55 V to 13 V, the internal regulator is disabled. This reduces the power dissipation in the IC.

7.3.3 Regulation Comparator

The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high-side switch stays on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the high-side switch stays off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage is below 1.225 V at the end of each on-time, causing the high-side switch to turn on immediately after the minimum forced off-time of 144 ns. The high-side switch can be turned off before the on-time is complete if peak current in the inductor reaches the current limit threshold.

7.3.4 Overvoltage Comparator

The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62-V the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load changes suddenly. The high-side switch will not turn on again until the voltage at FB falls below 1.225 V.

7.3.5 On-Time Generator

The on-time for the LM34926 device is determined by the R_ON resistor, and is inversely proportional to the input voltage (V_IN), resulting in a nearly constant frequency as V_IN is varied over its range. The on-time equation for the LM34926 is determined be Equation 3.

Equation 3.

See Figure 5. R_ON should be selected for a minimum on-time (at maximum V_IN) greater than 100 ns, for proper operation. This requirement limits the maximum frequency for each application.

7.3.6 Current Limit

The LM34926 device contains an intelligent current limit off-timer. If the current in the buck switch exceeds
575 mA, the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-time is controlled by the FB voltage and the input voltage V_IN. As an example, when FB = 0 V and V_IN = 48 V, a maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of
100 V.

In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and start-up time. The off-time is calculated from Equation 4.

Equation 4.

The current limit protection feature is peak limited, the maximum average output will be less than the peak.

7.3.7 N-Channel Buck Switch and Driver

The LM34926 device integrates an N-channel buck switch and associated floating high voltage gate driver. The gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage diode. A 0.01-uF ceramic capacitor connected between the BST and SW pins provides the voltage to the driver during the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges from V_CC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle to recharge the bootstrap capacitor.

7.3.8 Synchronous Rectifier

The LM34926 device provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for the inductor current to flow when the high-side MOSFET is turned off.

The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous conduction mode even during light loads which would otherwise result in discontinuous operation. This feature specifically allows the user to design a secondary regulator using a transformer winding off the main inductor to generate the alternate regulated output voltage.

7.3.9 Undervoltage Detector

The LM34926 device contains a dual-level UVLO circuit. A summary of threshold voltages and operational states is provided in Device Functional Modes. When the UVLO pin voltage is below 0.66 V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66 V but less than 1.225 V, the controller is in standby mode. In standby mode the V_CC bias regulator is active while the regulator output is disabled. When the V_CC pin exceeds the V_CC undervoltage thresholds and the UVLO pin voltage is greater than 1.225 V, normal operation begins. An external set-point voltage divider from V_IN to GND can be used to set the minimum operating voltage of the regulator.

UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance R_UV2.

If the UVLO pin is wired directly to the V_IN pin, the regulator will begin operation once the V_CC undervoltage is satisfied.

Figure 10. UVLO Resistor Setting

7.3.10 Thermal Protection

The LM34926 device should be operated so the junction temperature does not exceed 150°C during normal operation. An internal Thermal Shutdown circuit is provided to protect the LM34926 device in the event of a higher than normal junction temperature. When activated, typically at 165°C, the controller is forced into a low-power reset state, disabling the buck switch and the V_CC regulator. This feature prevents catastrophic failures from accidental device overheating. When the junction temperature falls below 145°C (typical hysteresis = 20°C), the V_CC regulator is enabled, and normal operation is resumed.

7.3.11 Ripple Configuration

LM34926 uses constant on-time (COT) control scheme, in which the on-time is terminated by an on-timer, and the off-time is terminated by the feedback voltage (V_FB) falling below the reference voltage (V_REF). Therefore, for stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during the off-time. Furthermore this change in feedback voltage (ΔV_FB) during off-time must be large enough to suppress any noise component present at the feedback node.

Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output voltage ripple has two components:

1. Capacitive ripple caused by the inductor current ripple charging and discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.

The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and decreases monotonically during off-time. The resistive ripple must exceed the capacitive ripple at the output node (V_OUT) for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off-time.

Type 3 ripple method uses R_r and C_r and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is AC-coupled using C_ac to the feedback node (FB). Because this circuit does not use the output voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs (SNVA166) for more details for each ripple generation method.

Table 1. Ripple Configuration

TYPE 1 LOWEST COST CONFIGURATION	TYPE 2 REDUCED RIPPLE CONFIGURATION	TYPE 3 MINIMUM RIPPLE CONFIGURATION

7.3.12 Soft Start

A soft-start feature can be implemented with the LM34926 device using an external circuit. As shown in Figure 11, the soft-start circuit consists of one capacitor C₁, two resistors R₁ and R₂, and a diode D. During the initial start-up, the VCC voltage is established before the V_OUT voltage. Capacitor C₁ is discharged and diode D is thereby forward biased to pull up the FB voltage. The FB voltage exceeds the reference voltage (1.225 V) and switching is therefore disabled. As capacitor C₁ charges, the voltage at node B gradually decreases and switching commences. V_OUT will gradually rise to maintain the FB voltage at the reference voltage. Once the voltage at node B is less than a diode drop above the FB voltage, the soft-start sequence is finished and D is reverse-biased.

During the initial part of the start-up, the FB voltage can be approximated as shown in Equation 5. The effect of R₁ has been ignored to simplify the calculation.

Equation 5.

C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 when the input voltage experiences a momentary drop to initialize the soft-start sequence.

To achieve the desired soft start, the following design guidance is recommended:

1. R₂ is selected so that V_FB is higher than 1.225 V for a V_CC of 4.5 V, but is lower than 5 V when V_CC is 8.55 V. If an external V_CC is used, V_FB should not exceed 5 V at maximum V_CC.
2. C₁ is selected to achieve the desired start-up time which can be determined from .

3. R₁ is used to maintain the node B voltage at zero after the soft start is finished. A value larger than the feedback resistor divider is preferred. The effect of resistor R1 is ignored.

Using the component values shown in Figure 12, selecting C₁ = 1 uF, R₂ = 1 kΩ, R₁ = 30 kΩ results in a soft-start time of about 2 ms.

Figure 11. Soft-Start Circuit

Table 2. UVLO Mode