SNVSBU7 September   2020 LM34966-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 8.3.3  Soft Start (SS Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (UVLO/SYNC/EN Pin)
      6. 8.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 8.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 8.3.9  Power-Good Indicator (PGOOD Pin)
      10. 8.3.10 Hiccup Mode Overload Protection
      11. 8.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (GATE Pin)
      13. 8.3.13 Overvoltage Protection (OVP)
      14. 8.3.14 Thermal Shutdown (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Power-On Hours (POH)
    2. 9.2 Application Information
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Custom Design With WEBENCH® Tools
        2. 9.3.2.2 Recommended Components
        3. 9.3.2.3 Inductor Selection (LM)
        4. 9.3.2.4 Output Capacitor (COUT)
        5. 9.3.2.5 Input Capacitor
        6. 9.3.2.6 MOSFET Selection
        7. 9.3.2.7 Diode Selection
        8. 9.3.2.8 Efficiency Estimation
      3. 9.3.3 Application Curve
    4. 9.4 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.9 Power-Good Indicator (PGOOD Pin)

The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches to a high impedance open-drain state when the FB pin voltage is greater than the feedback under voltage threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The recommended minimum pullup resistor value is 10 kΩ.

Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater than VBIAS+ 0.3 V.