SNVS653E July   2011  – August 2015 LM3532

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C-Compatible Timing Specifications (SCL, SDA)
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 40-V Boost Converter
      2. 7.3.2 Hardware Enable Input
      3. 7.3.3 Feedback Enable
      4. 7.3.4 LM3532 Current Sink Configuration
      5. 7.3.5 PWM Inputs
      6. 7.3.6 Full-Scale LED Current
      7. 7.3.7 Interrupt Output
      8. 7.3.8 Protection Features
        1. 7.3.8.1 Overvoltage Protection
        2. 7.3.8.2 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1  LED Current Ramping
      2. 7.4.2  Start-up and Shutdown Current Ramping
      3. 7.4.3  Run-Time Ramp Rates
      4. 7.4.4  LED Current Mapping Modes
      5. 7.4.5  Exponential Current Mapping Mode
      6. 7.4.6  Linear Current Mapping
      7. 7.4.7  LED Current Control
        1. 7.4.7.1 I2C Current Control
        2. 7.4.7.2 I2C Current Control With PWM
      8. 7.4.8  Assigning and Enabling a PWM Input
      9. 7.4.9  Enabling a Current Sink
      10. 7.4.10 Ambient Light Sensor Current Control
        1. 7.4.10.1  ALS Resistors
        2. 7.4.10.2  Ambient Light Zone Boundaries
        3. 7.4.10.3  Ambient Light Zone Hysteresis
        4. 7.4.10.4  PWM Enabled for a Particular Zone
        5. 7.4.10.5  ALS Operation
        6. 7.4.10.6  ALS Input Select and ALS ADC Input
        7. 7.4.10.7  ALS ADC Readback
        8. 7.4.10.8  ALS Averaging
        9. 7.4.10.9  ALS ADC Average Readback
        10. 7.4.10.10 Initializing the ALS
        11. 7.4.10.11 ALS Operation
        12. 7.4.10.12 Direct ALS Control
      11. 7.4.11 Down Delay
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Start and Stop Conditions
        2. 7.5.1.2 I2C-Compatible Address
        3. 7.5.1.3 Transferring Data
    6. 7.6 Register Maps
      1. 7.6.1  Output Configuration
      2. 7.6.2  Start-up/Shutdown Ramp Rate
      3. 7.6.3  Run-Time Ramp Rate
      4. 7.6.4  Control A PWM
      5. 7.6.5  Control B PWM
      6. 7.6.6  Control C PWM
      7. 7.6.7  Control A Brightness Configuration
      8. 7.6.8  Control B Brightness Configuration
      9. 7.6.9  Control C Brightness Configuration
      10. 7.6.10 Control A, B, and C Full-Scale Current
      11. 7.6.11 Feedback Enable
      12. 7.6.12 Control Enable
      13. 7.6.13 ALS1 and ALS2 Resistor Select
      14. 7.6.14 ALS Down Delay
      15. 7.6.15 ALS Configuration
      16. 7.6.16 ALS Zone Readback / Information
      17. 7.6.17 ALS Zone Boundaries
      18. 7.6.18 Zone Target Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Capacitor Selection
        3. 8.2.2.3 Diode Selection
        4. 8.2.2.4 Maximum Output Power
          1. 8.2.2.4.1 Peak Current Limited
          2. 8.2.2.4.2 Output Voltage Limited
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Inductor Placement
      4. 10.1.4 Input Capacitor Selection and Placement
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The LM3532 contains an inductive boost converter which sees a high switched voltage (up to 40 V) at the SW pin, and a step current (up to 1 A) through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = CdV/dt). The large step current through the diode, and the output capacitor can cause a large voltage spike at the SW pin and the OVP pin due to parasitic inductance in the step current conducting path (V = LdI/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise. Figure 44 highlights these two noise generating components.

LM3532 301154101.gifFigure 44. LM3532'S Boost Converter Showing Pulsed Voltage at SW (High Dv/Dt) and
Current Through Schottky and COUT (High Di/Dt)

The following lists the main (layout sensitive) areas of the LM3532 in order of decreasing importance:

    Output Capacitor

  • Schottky Cathode to COUT+
  • COUT− to GND


    • Schottky Diode

  • SW Pin to Schottky Anode
  • Schottky Cathode to COUT+


    • Inductor

  • SW Node PCB capacitance to other traces


    • Input Capacitor

  • CIN+ to IN pin
  • CIN− to GND

10.1.1 Output Capacitor Placement

The output capacitor is in the path of the inductor current discharge current. As a result, COUT sees a high current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Typical turnoff/turnon times are around 5 ns. Any inductance along this series path from the cathode of the diode through COUT and back into the LM3532's GND pin contributes to voltage spikes (VSPIKE = LPX × dI/dt) at SW and OUT which can potentially over-voltage the SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close as possible to the Cathode of the Schottky diode and COUT− must be connected as close as possible to the LM3532's GND bump. The best placement for COUT is on the same layer as the LM3532 to avoid any vias that add extra series inductance (see Layout Examples).

10.1.2 Schottky Diode Placement

The Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any inductance in series with the diode causes a voltage spike (VSPIKE = LPX × dI/dt) at SW and OUT which can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor and into GND. Connecting the anode of the diode as close as possible to the SW pin and the cathode of the diode as close as possible to COUT+ reduces the inductance (LPX) and minimize these voltage spikes (see Layout Examples).

10.1.3 Inductor Placement

The node where the inductor connects to the LM3532’s SW bump has 2 issues. First, a large switched voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause large voltage drops that negatively affect efficiency.

To reduce the capacitively coupled signal from SW into nearby traces, the SW bump to inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, other nodes need to be routed away from SW and not directly beneath. This is especially true for high impedance nodes that are more susceptible to capacitive coupling such as (SCL, SDA, HWEN, PWM, and possibly ASL1 and ALS2). A GND plane placed directly below SW helps isolate SW and dramatically reduce the capacitance from SW into nearby traces.

To limit the trace resistance of the VBATT to inductor connection and from the inductor to SW connection, use short, wide traces (see Layout Examples).

10.1.4 Input Capacitor Selection and Placement

The input bypass capacitor filters the inductor current ripple, and the internal MOSFET driver currents during turn on of the power switch.

The driver current requirement can be a few hundred milliamps with 5 ns rise and fall times. This appears as high dI/dt current pulses coming from the input capacitor each time the switch turns on. Close placement of the input capacitor to the IN pin and to the GND pin is critical because any series inductance between IN and CIN+ or CIN− and GND can create voltage spikes that could appear on the VIN supply line and in the GND plane.

Close placement of the input bypass capacitor at the input side of the inductor is also critical. The source impedance (inductance and resistance) from the input supply, along with the input capacitor of the LM3532, form a series RLC circuit. If the output resistance from the source (RS) is low enough the circuit is underdamped and has a resonant frequency (typically the case). Depending on the size of LS the resonant frequency could occur below, close to, or above the LM3532's switching frequency. This can cause the supply current ripple to be:

  • Approximately equal to the inductor current ripple when the resonant frequency occurs well above the LM3532's switching frequency;
  • Greater then the inductor current ripple when the resonant frequency occurs near the switching frequency; or
  • Less then the inductor current ripple when the resonant frequency occurs well below the switching frequency.

Figure 45 shows this series RLC circuit formed from the output impedance of the supply and the input capacitor. The circuit is re-drawn for the AC case where the VIN supply is replaced with a short to GND and the LM3532 + Inductor is replaced with a current source (ΔIL).

Equation 1 is the criteria for an underdamped response. Equation 2 is the resonant frequency. Equation 3 is the approximated supply current ripple as a function of LS, RS, and CIN.

As an example, consider a 3.6-V supply with 0.1 Ω of series resistance connected to CIN through 50 nH of connecting traces. This results in an underdamped input filter circuit with a resonant frequency of 712 kHz. Because the switching frequency lies near to the resonant frequency of the input RLC network, the supply current is probably larger then the inductor current ripple. In this case, using equation 3 from Figure 45, the supply current ripple can be approximated as 1.68 times the inductor current ripple. Increasing the series inductance (LS) to 500 nH causes the resonant frequency to move to around 225 kHz and the supply current ripple to be approximately 0.25 times the inductor current ripple.

LM3532 301154102.gifFigure 45. Input RLC Network

10.2 Layout Examples

Figure 46 and Figure 47 show example layouts which apply the required (proper) layout guidelines. These figures should be used as guides for laying out the LM3532's boost circuit.

LM3532 30115485.gifFigure 46. Layout Example 1
LM3532 30115486.gifFigure 47. Layout Example 2