SNVSAJ8D
February 2016 – March 2018
LM36273
PRODUCTION DATA.
1
Features
2
Applications
Simplified Schematic
3
Description
Backlight Efficiency, 3P7S
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Timing Requirements (Fast Mode)
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Features Description
7.3.1
Enabling the LM36273
7.3.2
Backlight
7.3.2.1
Current Sink Enable
7.3.2.2
Brightness Mapping
7.3.2.2.1
Linear Mapping
7.3.2.2.2
Exponential Mapping
7.3.2.3
Backlight Brightness Control Modes
7.3.2.3.1
I2C Brightness Control (PWM Pin Disabled)
7.3.2.3.2
I2C × PWM Brightness Control (PWM Pin Enabled)
7.3.2.3.2.1
PWM Ramper
7.3.2.4
Boost Switching Frequency
7.3.2.4.1
Minimum Inductor Select
7.3.2.5
Boost Feedback Gain Select
7.3.2.6
Auto Switching Frequency
7.3.2.7
PWM Input
7.3.2.7.1
PWM Sample Frequency
7.3.2.7.1.1
PWM Resolution and Input Frequency Range
7.3.2.7.1.2
PWM Sample Rate and Efficiency
7.3.2.7.1.2.1
PWM Sample Rate Example
7.3.2.7.2
PWM Hysteresis
7.3.2.7.3
PWM Step Response
7.3.2.7.4
PWM Timeout
7.3.2.7.5
PWM-to-Digital Code Readback
7.3.2.8
Regulated Headroom Voltage
7.3.2.9
Backlight Fault Protection and Faults
7.3.2.9.1
Backlight Overvoltage Protection (OVP)
7.3.2.9.2
Backlight Overcurrent Protection (OCP)
7.3.3
LCM Bias
7.3.3.1
Display Bias Boost Converter (VVPOS, VVNEG)
7.3.3.2
Auto Sequence Mode
7.3.3.3
Wake-up Mode
7.3.3.3.1
Wake1 Mode
7.3.3.3.2
Wake2 Mode
7.3.3.4
Active Discharge
7.3.3.5
LCM Bias Protection and Faults
7.3.3.5.1
LCM Overvoltage (OVP) Protection
7.3.3.5.2
VPOS Short-Circuit Protection
7.3.3.5.3
VNEG Short-Circuit Protection
7.3.4
Software Reset
7.3.5
HWEN Input
7.3.6
Thermal Shutdown (TSD)
7.4
Device Functional Modes
7.4.1
Modes of Operation
7.5
Programming
7.5.1
I2C-Compatible Serial Bus Interface
7.5.1.1
Interface Bus Overview
7.5.1.2
Data Transactions
7.5.1.3
Acknowledge Cycle
7.5.1.4
Acknowledge After Every Byte Rule
7.5.1.5
Addressing Transfer Formats
7.5.1.6
Register Programming
7.6
Register Maps
7.6.1
Revision Register (Address = 0x01)[Reset = 0x01]
Table 11.
Revision Register Field Descriptions
7.6.2
Backlight Configuration1 Register (Address = 0x02)[Reset = 0x28]
Table 12.
Backlight Configuration 1 Register Field Descriptions
7.6.3
Backlight Configuration 2 Register (Address = 0x03)[Reset = 0x8D]
Table 13.
Backlight Configuration 2 Register Field Descriptions
7.6.4
Backlight Brightness LSB Register (Address = 0x04)[Reset = 0x07]
Table 14.
Backlight Brightness LSB Register Field Descriptions
7.6.5
Backlight Brightness MSB Register (Address = 0x05)[Reset = 0xFF]
Table 15.
Backlight Brightness MSB Register Field Descriptions
7.6.6
Backlight Auto-Frequency Low Threshold Register (Address = 0x06)[Reset = 0x00]
Table 16.
Backlight Auto-Frequency Low Threshold Field Descriptions
7.6.7
Backlight Auto-Frequency High Threshold Register (Address = 0x07)[Reset = 0x00]
Table 17.
Backlight Auto-Frequency High Threshold Field Descriptions
7.6.8
Backlight Enable Register (Address = 0x08)[Reset = 0x00]
Table 18.
Backlight Enable Register Field Descriptions
7.6.9
Bias Configuration 1 Register (Address = 0x09)[Reset = 0x18]
Table 19.
Bias Configuration 1 Register Field Descriptions
7.6.10
Bias Configuration 2 register (Address = 0x0A)[Reset = 0x11]
Table 20.
Bias Configuration 2 Register Field Descriptions
7.6.11
Bias Configuration 3 Register (Address = 0x0B)[Reset = 0x00]
Table 21.
Bias Configuration 3 Register Field Descriptions
7.6.12
LCM Boost Bias Register (Address = 0x0C)[Reset = 0x28]
Table 22.
LCM Boost Bias Register Field Descriptions
7.6.13
VPOS Bias Register (Address = 0x0D)[Reset = 0x1E]
Table 23.
VPOS Bias Register Field Descriptions
7.6.14
VNEG Bias Register (Address = 0x0E)[Reset = 0x1C]
Table 24.
VNEG Bias Register Field Descriptions
7.6.15
Flags Register (Address = 0x0F)[Reset = 0x00]
Table 25.
Flags Register Field Descriptions
7.6.16
Option 1 Register (Address = 0x10)[Reset = 0x06]
Table 26.
Option 1 Register Field Descriptions
7.6.17
Option 2 Register (Address = 0x11)[Reset = 0x35]
Table 27.
Option 2 Register Field Descriptions
7.6.18
PWM-to-Digital Code Readback LSB Register (Address = 0x12)[Reset = 0x00]
Table 28.
PWM-to-Digital Code Readback LSB Register Field Descriptions
7.6.19
PWM-to-Digital Code Readback MSB Register (Address = 0x13)[Reset = 0x00]
Table 29.
PWM-to-Digital Code Readback MSB Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Component Selection
8.2.2.1.1
Inductor Selection
8.2.2.1.2
Boost Output Capacitor Selection
8.2.2.1.3
Input Capacitor Selection
8.2.3
Application Curves
8.2.3.1
Backlight Curves
8.2.3.1.1
Two LED Strings
8.2.3.1.2
Three LED Strings
8.2.3.2
LCM Bias Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Development Support
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Community Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YFF|24
MXBG162A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snvsaj8d_oa
snvsaj8d_pm
7.5.1
I
2
C-Compatible Serial Bus Interface