SNVS834 August   2014 LM3631

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements (SDA, SCL)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1  Backlight
        1. 8.3.1.1 Backlight Brightness Control
          1. 8.3.1.1.1 LED Current With Brightness Selection '00'
          2. 8.3.1.1.2 LED Current With Brightness Selection '01'
          3. 8.3.1.1.3 LED Current With Brightness Selections '10' and '11'
        2. 8.3.1.2 Linear Slope and Advanced Slope
        3. 8.3.1.3 Mapper
        4. 8.3.1.4 PWM Detector and PWM Input
      2. 8.3.2  Backlight Boost Converter
        1. 8.3.2.1 Headroom Voltage
        2. 8.3.2.2 Automatic Switching Frequency Shift
        3. 8.3.2.3 Inductor Select Bit
        4. 8.3.2.4 PI-Compensator
      3. 8.3.3  Backlight Protection and Faults
        1. 8.3.3.1 Overvoltage Protection (OVP) and Open-Load Fault Protection
        2. 8.3.3.2 Overcurrent Protection (OCP) and Overcurrent Protection Fault
          1. 8.3.3.2.1 Overcurrent Protection Fault Flag (BL_OCPFLT)
          2. 8.3.3.2.2 Short Circuit Fault Flag (BL_SCFLT)
      4. 8.3.4  LCD Bias
        1. 8.3.4.1 Display Bias Power (VPOS, VNEG, VOREF)
        2. 8.3.4.2 Display Bias Power Sequencing (VPOS, VNEG, VOREF, VCONT)
          1. 8.3.4.2.1 Start-Up and Shutdown Delays
          2. 8.3.4.2.2 Special Conditions During Display Bias Power Sequencing
        3. 8.3.4.3 Active Discharge
        4. 8.3.4.4 LCD Bias Protection
      5. 8.3.5  Display Controller Power (VLDO_CONT)
      6. 8.3.6  RESET Register
      7. 8.3.7  nRST Input
      8. 8.3.8  FLAG Pin
      9. 8.3.9  Power-Good Flag
      10. 8.3.10 OTP_SEL Pin
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Bus Interface
        1. 8.5.1.1 Interface Bus Overview
        2. 8.5.1.2 Data Transactions
        3. 8.5.1.3 Acknowledge Cycle
        4. 8.5.1.4 Acknowledge After Every Byte Rule
        5. 8.5.1.5 Addressing Transfer Formats
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Components
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Boost Output Capacitor Selection
        4. 9.2.2.4 Backlight Boost Diode Selection
        5. 9.2.2.5 Charge Pump Capacitor Selection
        6. 9.2.2.6 LDO Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
Voltage on VIN, nRST, LCD_EN, PWM, SCL, SDA, FLAG, LDO_CONT, OTP_SEL –0.3 6 V
Voltage on BST_SW, BST_OUT, LDO_VPOS, LDO_OREF, C1 –0.3 7 V
Voltage on CP_VNEG, C2 –7.0 0.3 V
Voltage on SW, VOUT, LED1, LED2 –0.3 30 V
Continuous power dissipation Internally limited
TJ(MAX) Maximum junction temperature 150 °C
TSOLDERING Note(2)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For detailed soldering specifications and information, please refer to Texas Instruments Application Note 1112: DSBGA Wafer Level Chip Scale Package (AN-1112).

7.2 Handling Ratings

PARAMETER MIN MAX UNIT
Tstg Storage temperature range –45 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins except SW(1) –1000 1000 V
Human body model (HBM), SW pin –600 600
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2.7 3.7 5 V
Voltage on nRST, LCD_EN, PWM, SCL, SDA, FLAG, LDO_CONT, OTP_SEL 0 VIN + 0.3V with 5V max V
Voltage on LDO_VPOS, LDO_OREF, C1 0 6.5 V
Voltage on BST_SW, BST_OUT 0 7 V
Voltage on CP_VNEG, C2 –6.5 0 V
Voltage on SW, VOUT, LED1, LED2 0 29 V
TA Operating ambient temperature (1) –40 85 °C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

7.4 Thermal Information

THERMAL METRIC(1) DSBGA UNIT
(20 PINS)
RθJA Junction-to-ambient thermal resistance 63.5 °C/W
RθJC Junction-to-case (top) thermal resistance 0.3
RθJB Junction-to-board thermal resistance 9.4
ΨJT Junction-to-top characterization parameter 1.6
ΨJB Junction-to-board characterization parameter 9.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), VIN = 3.6 V, VPOS = VOREF = 5.4 V, VNEG = –5.4 V, VBST = 5.7 V, VCONT = 3.3V.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
CURRENT CONSUMPTION
ISD Shutdown current nRST = LOW, LCD_EN = LOW 1 µA
IQ Quiescent current, device not switching nRST = HIGH, LCD_EN = LOW, 2.7 V ≤ VIN ≤ 5 V 60 µA
ILCD_EN nRST = HIGH, LCD_EN = HIGH, 2.7 V ≤ VIN ≤ 5 V, no load, Backlight disabled 1 mA
DEVICE PROTECTION
UVLO Undervoltage lockout VIN decreasing 2.5 V
VIN increasing 2.6 V
TSD Thermal shutdown(2) 140 °C
TSD(hyst) Hysteresis(2) 20 °C
LED CURRENT SINKS
ILED1/2 Minimum output current Brightness code 0x001 50 µA
Maximum output current Brightness code 0x7FF, exponential mapping 25 mA
Maximum output current Brightness code 0x7FF, linear mapping 25.3 mA
IACCURACY Absolute LED current accuracy (1) 2.7 V ≤ VIN ≤ 5.0 V, LED Currents 0.05 mA, 1 mA, 5 mA, 25 mA –3% 3%
IMATCH LED1 to LED2 current matching (1) 2.7 V ≤ VIN ≤ 5.0 V, LED Currents 0.05 mA, 1 mA, 5 mA, 25 mA 0% 3%
VHR_MIN Current sink saturation voltage ILED = 95% of 5 mA 30 50 mV
BACKLIGHT BOOST CONVERTER
VOVP_BL Backlight boost output overvoltage protection 2.7 V ≤ VIN ≤ 5 V, 29-V Option 28.8 V
ηLED_DRIVE LED drive efficiency (2) ILED = 10 mA/string, 2P6S LED configuration
1235AS-H-220M Inductor		 88%
VHR Regulated current sink headroom voltage ILED = 25 mA 250 mV
ILED = 5 mA 100 mV
RDSON NMOS switch on resistance ISW = 250 mA 0.5 Ω
ICL Selectable NMOS switch current limit 900-mA setting 900 mA
ƒSW Switching frequency 500-kHz mode 450 500 550 kHz
1-MHz mode 900 1000 1100
DMAX Maximum duty cycle 94%
LCD BIAS BOOST CONVERTER
VOVP_BST LCD bias boost output overvoltage protection 6.8 V
ƒSW_BST Switching frequency (2) Load current 100mA 2500 kHz
VBST Minimum Bias boost output voltage LCD_BST_OUT = 000000b 4.5 V
Maximum Bias boost output voltage LCD_BST_OUT = 100101b 6.35
Output voltage step size 50 mV
Peak-to-peak ripple voltage (3) ILOAD = 50 mA, CBST = 10 µF 50 mVpp
BST_OUT line transient response (3) VIN + 500 mVp-p AC square wave, Tr = 100 mV/µs, 200 Hz, 12.5% Duty, ILOAD 5 mA, CIN = 10 µF, CBST = 10 µF –50 ±25 50 mV
BST_OUT load transient response (3) Load current step 0 mA - 150 mA, TRISE/FALL = 100 mA/µs, CIN = 10 µF, CBST = 10 µF –150 150 mV
ICL_BST Valley current limit 1000 mA
RDSON_BST High-side MOSFET on resistance TA = 25°C 170 mΩ
Low-side MOSFET on resistance TA = 25°C 290
ηBST Efficiency (2) 80 mA < IBST < 200 mA 92%
tST_BST Start-up time (BST_OUT), VBST_OUT = 10% to 90% (3) CBST = 20 µF 1000 µs
LCD POSITIVE BIAS OUTPUT (LDO_VPOS)
VPOS Minimum output voltage LDO_VPOS_TARGET = 000000b 4.0 V
Maximum output voltage LDO_VPOS_TARGET = 101000b 6.0 V
Output voltage step size 50 mV
Output voltage accuracy Output voltage = 5.4 V, ILOAD= 1 mA –1.5% 1.5%
LDO_VPOS line transient response (3) VIN + 500 mVp-p AC square wave, Tr = 100 mV/µs, 200 Hz, ILOAD 25 mA, CIN = 10 µF –25 25 mV
LDO_VPOS load transient response (3) 5 mA to 100 mA load transient, TRISE/FALL = 2 µs , CVPOS = 10 µF –100 100 mV
DC load regulation (3) 1 mA ≤ ILOAD ≤ 100 mA 20 mV
PGRISING Power-good threshold, voltage increasing % of target VPOS 95%
PGFALLING Power-good threshold, voltage decreasing % of target VPOS 90%
IPOS_MAX Maximum output current 100 mA
ICL_VPOS Output current limit 200 mA
IRUSH_PK_VPOS Peak start-up inrush current (3) VBST = 6.3 V, VPOS = 6 V, CVPOS = 10 µF 500 mA
VDO_VPOS LDO_VPOS dropout voltage (4) ILOAD = 100 mA, VPOS = 4 V 80 mV
PSRRVPOS Power supply rejection ratio, LDO_VPOS (3) ƒ = 10 Hz to 500 kHz, ILOAD= 50 mA, VBST to VPOS, 300 mV minimum headroom 25 dB
tST_VPOS Start-up time LDO_VPOS, VLDO_VPOS = 10% to 90% (3) CVPOS = 10 µF 1 ms
RPD_VPOS Output pull-down resistor, LDO_VPOS LDO_VPOS pull-down enabled, LDO_VPOS disabled 52 80 110 Ω
LCD NEGATIVE BIAS OUTPUT (CP_VNEG)
VOVP_VNEG LCD bias negative charge-pump output overvoltage protection Below VNEG output voltage target –250 mV
VSHORT_VNEG LCD bias negative charge-pump output short circuit protection –1 V
VNEG Minimum output voltage CP_VNEG_TARGET = 101000b –6.0 V
Maximum output voltage CP_VNEG_TARGET = 000000b –4.0 V
Output voltage step size 50 mV
Output accuracy Output voltage = –5.4V –1.5% 1.5%
Peak-to-peak ripple voltage (3) ILOAD = 50 mA,
CVNEG = 10 µF		 60 mVpp
CP_VNEG line transient response (3) VIN + 500 mVp-p AC square wave, 100 mV/µs 200 Hz, 12.5% DS at 5 mA –50 ±25 50 mV
CP_VNEG load transient response (3) 5 mA to 50 mA load transient, TRISE/FALL = 1 µs, CVNEG = 10 µF –100 100 mV
PGRISING Power good increasing % of Target VNEG 95%
PGFALLING Power good decreasing % of Target VNEG 90%
ηCP Efficiency(2) VIN = 3,7V, VBST = 5,7V VNEG = -5.4V, 20mA < ILOAD < 80mA 92%
INEG_MAX Maximum output current (3) VIN = 3.7 V, VBST = 5.6 V,
VNEG = –5.4V		 50 mA
VIN = 3.7 V, VBST = 5.7 V,
VNEG = –5.4 V		 80 mA
ICL_VNEG Output current limit (3) 150 mA
tST_VNEG Start-up time, CP_VNEG, VCP_VNEG = 10 % to 90 % (3) VNEG = –6V, CVNEG = 10 µF 1 ms
RPU_VNEG Output pull-up resistor, CP_VNEG (3) CP_VNEG Pull-Up Enabled, CP_VNEG Disabled, VBST > 4.8V 30 40 Ω
LCD GAMMA REFERENCE OUTPUT (LDO_OREF)
VOREF Minimum Output voltage LDO_OREF_TARGET = 000000b 4.0 V
Maximum Output voltage LDO_OREF_TARGET = 101000b 6.0 V
Output voltage step size 50 mV
Output accuracy ILOAD_LDO_OREF < 5 mA, VOREF= 5.4V –1.5% 1.5%
LDO_OREF line transient response (3) VIN + 500 mVp-p AC Square Wave, 100 mV/µs 200 Hz at 5 mA, CIN = 10 µF –50 50 mV
LDO_OREF load transient (3) 5 mA to 50 mA load transient @ 2 µs TRISE/FALL, CIN = 10 µF –50 50 mV
DC load regulation (3) 1 mA ≤ ILOAD_LDO_OREF ≤ ILOAD_LDO_OREF_MAX 20 mV
PGRISING Power good increasing % of target VLDO_OREF 95%
PGFALLING Power good decreasing % of target VLDO_OREF 90%
IOREF_MAX Maximum output current 50 mA
ICL_OREF Output current limit 80 mA
IRUSH_PK_OREF Peak start-up inrush current (3) VBIASBST = 5.8 V, VOREF = 5.5 V, COREF = 10 µF 250 mA
VDO_OREF LDO_OREF dropout voltage (5) ILOAD_LDO_OREF = ILOAD_LDO_OREF_MAX, VLDO_OREF = 4.0 V 80 mV
PSRROREF Power supply rejection ratio, LDO_OREF (3) F = 10 Hz to 500 kHz @ Imax/2, VBST_OUT to VLDO_OREF, 300 mV minimum headroom 25 dB
tST_OREF Start-up time, LDO_OREF, VLDO_OREF = 10% to 90% (3) COREF = 10 µF, VLDO_OREF = 5.5 V 1 ms
RPD_OREF Output pull-down resistor, LDO_OREF LDO_OREF pull-down enabled, LDO_OREF disabled 130 200 270 Ω
LCD CONTROLLER SUPPLY OUTPUT (LDO_CONT)
VCONT Output voltage LDO_CONT_VOUT = 00 1.8 V
LDO_CONT_VOUT = 01 2.3
LDO_CONT_VOUT = 10 2.8
LDO_CONT_VOUT = 11 3.3
Output accuracy Output Voltage = 1.8 V, 1-mA load –2% 2%
LDO_CONT line transient response (3) VIN + 500 mVp-p AC Square Wave, 100 mV/µs 200 Hz at 5 mA –50 50 mV
LDO_CONT load transient response (3) 5-mA to 80-mA load transient @ 2 µs TRISE/FALL –50 50 mV
DC load regulation (3) 1 mA ≤ ILOAD_LDO_CONT ≤ 80 mA 20 mV
ICONT_MAX Maximum output current 80 mA
ICL_CONT Output current limit 130 mA
VDO_CONT LDO_CONT dropout voltage (6) ILOAD = 80 mA, VCONT = 3.3 V 80 mV
PSRRLDO_CONT Power supply rejection ratio, LDO_CONT (3) F = 10 Hz to 500 kHz @ Imax/2 VIN to VLDO_CONT, 300-mV minimum headroom 25 dB
tST_CONT Start-up time, LDO_CONT, VCONT = 10% to 90% (3) VCONT = 1.8 V 1 ms
RPD_CONT Output pull-down resistor, LDO_CONT LDO_CONT pull-down enabled, LDO_CONT disabled 200 Ω
LOGIC INPUTS (PWM, NRST, LCD_EN, SCL, SDA, OTP_SEL)
VIL Input logic low 0 0.4 V
VIH Input logic high 1.2 VIN V
IINPUT Logic input current –1 1 µA
LOGIC OUTPUTS (SDA, FLAG)
VOL Output logic low IOL = 3 mA 0 0.4 V
ILEAKAGE Output leakage current 1 µA
PWM INPUT
ƒPWM_INPUT PWM input frequency 100 20000 Hz
tMIN Minimum PWM ON/OFF time 400 ns
tTIMEOUT PWM timeout(3) 24 ms
(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (LED1 and LED2), the following is determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of both outputs (AVG). Matching number is calculated: (MAX - MIN)/AVG. The typical specification provided is the most likely norm of the matching figure of all parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
(2) Typical value only for reference.
(3) Limits set by characterization and/or simulation only.
(4) VBST – VPOS when VPOS has dropped 100 mV below target.
(5) VBST – VOREF when VOREF has dropped 100 mV below target.
(6) VIN – VCONT when VCONT has dropped 100 mV below target.

7.6 I2C Timing Requirements (SDA, SCL) (1)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ƒSCL Clock frequency 400 kHz
1 Hold time (repeated) START condition 0.6 µs
2 Clock low time 1.3 µs
3 Clock high time 600 ns
4 Set-up time for a repeated START condition 600 ns
5 Data hold time 50 ns
6 Data set-up time 100 ns
7 Rise time of SDA and SCL 20 + 0.1Cb 300 ns
8 Fall time of SDA and SCL 15 + 0.1Cb 300 ns
9 Set-Up time between a STOP and a START condition 1.3 µs
Cb Capacitive load for each bus line 10 200 pF
(1) Limits set by characterization and/or simulation only
LM3631_I2C_Timing_Parameters.gifFigure 1. I2C Timing Parameters

7.7 Typical Characteristics

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
D001_SNVS834.gif
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
Figure 2. Backlight Boost Efficiency
D006_SNVS834.gif
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
Figure 4. Backlight Boost Efficiency
D008_SNVS834.gif
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
Figure 6. Backlight Boost Efficiency
D010_SNVS834.gif
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
Figure 8. Backlight Boost Efficiency
D003_SNVS834.gif
No load on LCD Bias
2P6S LED Configuration
500-kHz BL Boost SW Frequency
Figure 10. Device Current Consumption, Backlight Driving
D004_SNVS834.gif
2P6S LED Configuration
Figure 12. Backlight Boost Output Voltage
D013_SNVS834.gif
VLF403210MT-100M 10-µH Inductor
1-MHz BL Boost SW Frequency
2P6S LED Configuration
Figure 14. LED Current Matching
D015_SNVS834.gif
I2C Brightness Control
Figure 16. LED Current, Exponential Control
D017_SNVS834.gif
VBST set to 5.5 V
Figure 18. LCD Boost Efficiency
D019_SNVS834.gif
VNEG set to –5 V
Figure 20. VNEG Efficiency
D021_SNVS834.gif
VNEG set to –6 V
Figure 22. VNEG Efficiency
D023_SNVS834.gif
VBST set to 5.5 V
Figure 24. LCD Boost Load Regulation
D025_SNVS834.gif
VNEG set to –5 V
Figure 26. VNEG Load Regulation
D027_SNVS834.gif
VNEG set to –6 V
Figure 28. VNEG Load Regulation
D029_SNVS834.gif
VPOS set to 5.5 V
Figure 30. VPOS Load Regulation
D031_SNVS834.gif
VOREF set to 5 V
Figure 32. VOREF Load Regulation
D033_SNVS834.gif
VOREF set to 6 V
Figure 34. VOREF Load Regulation
D035_SNVS834.gif
VCONT set to 2.8 V
Figure 36. VCONT Load Regulation
D002_SNVS834.gif
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
Figure 3. Backlight Total Efficiency
D007_SNVS834.gif
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
Figure 5. Backlight Total Efficiency
D009_SNVS834.gif
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
Figure 7. Backlight Total Efficiency
D011_SNVS834.gif
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
Figure 9. Backlight Total Efficiency
D012_SNVS834.gif
No load on LCD Bias
2P6S LED Configuration
1-MHz BL Boost SW Frequency
Figure 11. Device Current Consumption, Backlight Driving
D005_SNVS834.gif
2P6S LED Configuration
Figure 13. LED Driver Headroom Voltage
D014_SNVS834.gif
I2C Brightness Control
Figure 15. LED Current, Linear Control
D016_SNVS834.gif
VBST set to 5.2 V
Figure 17. LCD Boost Efficiency
D018_SNVS834.gif
VBST set to 5.9 V
Figure 19. LCD Boost Efficiency
D020_SNVS834.gif
VNEG set to –5.5 V
Figure 21. VNEG Efficiency
D022_SNVS834.gif
VBST set to 5.2 V
Figure 23. LCD Boost Load Regulation
D024_SNVS834.gif
VBST set to 5.9 V
Figure 25. LCD Boost Load Regulation
D026_SNVS834.gif
VNEG set to –5.5 V
Figure 27. VNEG Load Regulation
D028_SNVS834.gif
VPOS set to 5 V
Figure 29. VPOS Load Regulation
D030_SNVS834.gif
VPOS set to 6 V
Figure 31. VPOS Load Regulation
D032_SNVS834.gif
VOREF set to 5.5 V
Figure 33. VOREF Load Regulation
D034_SNVS834.gif
VCONT set to 1.8 V
Figure 35. VCONT Load Regulation
D036_SNVS834.gif
VCONT set to 3.3 V
Figure 37. VCONT Load Regulation