7.3.1.1 Brightness Control

Brightness can be controlled either by the I²C brightness register or a combination of the external PWM control and the I²C brightness register. The backlight truth table is shown in Table 1.

When controlling brightness through I²C, registers 0x04 and 0x05 are used. Registers 0x04 and 0x05 hold the 11-bit brightness data. Register 0x04 contains the 3 LSBs, and register 0x05 contains the 8 MSBs. The LED current transitions to the new level after a write is done to register 0x05.

When controlling brightness through I²C, setting the brightness value to '0' shuts down the backlight. When controlling the brightness with PWM input, if PWM input is low for a certain period of time (25 ms typ.), the backlight shuts down. When using the combination of a PWM input and the I²C register, either option shuts down the backlight.

7.3.1.1.1 LED Current with PWM Disabled

When LED brightness is controlled from the I²C brightness registers, the 11-bit brightness data directly controls the LED current in BLED1 and BLED2. LED mapping can be selected as either linear or exponential. When this mode is selected, setting the PWM input to 0 does not disable the backlight.

With exponential mapping the 11-bit code-to-current response is approximated by the equation:

Equation 1. I_LED = 50 µA × 1.003040572^{I2C BRGT CODE} (for codes > 0)

Equation 1 is valid for I²C brightness codes between 1 and 2047. Code 0 disables the backlight. The Code-to-LED current response realizes a 0.304% change in LED current per LSB of brightness code.

Figure 22 and Figure 23 detail the exponential response of the LED current vs. brightness code. Figure 22 shows the response on a linear Y axis while Figure 23 shows the response on a log Y axis to show the low current levels at the lower codes.

Figure 22. Exponential Response of LED Current vs Brightness Code

Figure 23. Response of LED Current vs Brightness Code on a Log Y Axis

With linear mapping the 11-bit code to current response is approximated by the equation:

Equation 2. I_LED = 37.8055 µA + 12.1945 µA × I2C BRGT CODE (for codes > 0)

Equation 2 is valid for codes between 1 and 2047. Code 0 disables the backlight.

Figure 24. Brightness Control with PWM Bit Disabled

Figure 25. Brightness Control with PWM Bit Enabled

7.3.1.2 Sloper

The sloper smooths the transition from one brightness value to another. Slope time can be adjusted from 0 ms to 8000 ms with BL_TRANS[3:0] bits (see Table 9 for details). Transient time is used for sloping up and down. Transient time always remains the same regardless of the amount of change in brightness.

Figure 26. Sloper

7.3.1.3 Mapper

The mapper block maps the digital word set for the LED driver into current code. The user can select whether the mapping is exponential or linear with the BLED_MAP bit, register 0x02 bit[4].

Exponential control is tailored to the response of the human eye such that the perceived change in brightness during ramp up or ramp down is linear.

7.3.1.4 PWM Input

The PWM detector block measures the duty cycle in the PWM pin. The PWM period is measured from the rising edge to the next rising edge. PWM polarity can be changed with bit PWM_CONFIG, register 0x02 bit[3]. The sample rate for the PWM input can be set to 1 MHz or 4 MHz with bit PWM_FREQ, register 0x03 bit[2]. The choice of sample rate depends on three factors:

1. Required PWM resolution (input duty cycle to brightness code, with 11 bits max)
2. PWM input frequency
3. Efficiency

The PWM input block timeout is 25 ms for 1-MHz sampling frequency and 3 ms for 4-MHz sampling frequency, measured from the last rising edge. This should be taken into account for 0% and 100% brightness settings (for setting 100% brightness, the high level of PWM input signal should be greater than the PWM input timeout) and for selecting the minimum PWM input signal frequency.

7.3.1.5 PWM Minimum On/Off Time

The minimum PWM input signal allowed for low and high pulse width is 6 µs for 1-MHz sampling frequency and 1.5 µs for 4-MHz sampling frequency. This should be taken into account when selecting the PWM input signal frequency and maximum or minimum duty cycle. For example, if the PWM input signal frequency is 2 kHz (500 µs) and the 4-MHz sampling frequency is used, the maximum allowed on-time is: (500 – 1.5) µs = 498.5 µs. The maximum duty cycle allowed is 100 × (498.5/500) = 99.7%. By comparison, following similar calculations, with a PWM input signal frequency of 20 kHz the maximum allowed duty cycle is 97%.

7.3.1.6 PWM Resolution and Input Frequency Range

The PWM input resolution depends on the input signal frequency. To achieve the full 11-bit maximum resolution of PWM duty cycle to the LED brightness code, the input PWM duty cycle must be ≥ 11 bits, and the PWM sample period (1/f_SAMPLE) must be smaller than the minimum PWM input pulse width. Figure 27 shows the possible brightness code resolutions based on the input PWM frequency. The minimum recommended PWM frequency is 100 Hz, and maximum recommended PWM frequency is 20 kHz.

Figure 27. PWM Resolution and PWM Input Frequency

7.3.1.7 PWM Hysteresis

To prevent jitter in the input PWM signal from feeding through the PWM path and causing oscillations in the LED current, the LM3632A offers 4 programmable PWM hysteresis settings. Hysteresis works by forcing a specific number of 11-bit LSB code transitions to occur in the input duty cycle before the LED current changes. Table 9 describes the hysteresis. Hysteresis only applies during the change in direction of brightness currents. Once the change in direction has taken place, the PWM input must overcome the required LSB(s) of the hysteresis setting before the brightness change takes effect. Once the initial hysteresis has been overcome and the direction in brightness change remains the same, the PWM-to-current response changes with no hysteresis. Hysteresis is selected with the PWM_HYST bits, register 0x03 bits[1:0]. Changing the hysteresis value is recommended when PWM input frequency increases.

7.3.1.8 PWM Timeout

The LM3632A PWM timeout feature turns off the backlight boost output when the PWM input is enabled and there is no PWM pulse detected. The timeout duration depends on the PWM sample rate setting and defines the minimum supported PWM input frequency. Table 2 summarizes the sample rate, timeout, and minimum supported PWM frequency.

Table 2. PWM Timeout and Minimum Supported PWM Frequency vs PWM Sample Rate

7.3.1.9 Backlight Boost Converter

The high voltage required by the LED strings is generated with an asynchronous backlight boost converter. An adaptive voltage control loop automatically adjusts the output voltage based on the voltage over the LED drivers BLED1 and BLED2.

The LM3632A has two switching frequency modes, 500 kHz and 1 MHz. These are set via the BL_FREQ Select bit, register 0x03 bit[7]. Operation in low-frequency mode results in better efficiency at lighter load currents due to the decreased switching losses. Operation in high-frequency mode gives better efficiency at higher load currents due to the reduced inductor current ripple and the resulting lower conduction losses in the MOSFETs and inductor.

Figure 28. Backlight Boost Block Diagram

7.3.1.9.1 Headroom Voltage

In order to optimize efficiency, the LED driver-regulated headroom voltage (V_HR) changes with the programmed LED current. This allows for increased solution efficiency as the dropout voltage of the LED driver changes. Furthermore, in order to ensure that both current sinks remain in regulation when there is a mismatch in string voltages, the minimum headroom voltage between V_BLED1 and V_BLED2 becomes the regulation point for the boost converter. For example, if the LEDs connected to BLED1 require 25 V at the programmed current, and the LEDs connected to BLED2 require 25.5 V at the programmed current, the voltage at BLED1 is V_HR + 0.5 V, and the voltage at BLED2 is V_HR. In other words, the cathode of the highest voltage LED string becomes the boost output regulation point.

Figure 29. Regulated Headroom vs LED Current

7.3.2.1 Display Bias Boost Converter (V_VPOS, V_VNEG)

A single high-efficiency boost converter provides a positive voltage rail, V_{LCM_OUT}, which serves as the power rail for the LCM VPOS and VNEG outputs.

• The V_VPOS output LDO has a programmable range from 4 V up to 6 V with 50-mV steps and can supply up to 50 mA.
• The V_VNEG output is generated from a regulated, inverting charge pump and has an adjustable range of –6 V up to –4 V with 50-mV steps and a maximum load of 50 mA.

Boost voltage also has a programmable range from 4.5 V up to 6.4 V with 50-mV steps. Please refer to Table 19, Table 20 and Table 21 for V_{LCM_OUT}, V_VPOS and V_VNEG voltage settings. When selecting a suitable boost-output voltage, the following estimation can be used: V_{LCM_OUT} = max(V_VPOS, |V_VNEG|) + V_HR, where V_HR = 300 mV for lower currents and 400 mV for higher currents. When the device input voltage (V_IN) is greater than the programmed LCM boost output voltage, the boost voltage goes to V_IN + 100 mV. V_VPOS, and V_VNEG voltage settings cannot be changed while they are enabled. While the V_{LCM_OUT} target changes immediately upon a register write, V_VPOS and V_VNEG register setting targets take effect only after the outputs are disabled and re-enabled.

Figure 30. LCM Boost Block Diagram

Table 3. LCM Bias Truth Table

7.3.2.2 Auto Sequence Mode

If this mode is selected the LM3632A controls the turn-on and turn-off of VPOS and VNEG as shown in Figure 31.

Figure 31. Auto Sequence Timing

7.3.2.3 Wake-up Mode

If Wake-up mode is selected the LM3632A allows on/off control of both VPOS and VNEG with only one external pin (LCM_EN2). Any combination of VPOS, VNEG, or both can be turned on based on the state of bits VPOS_EN and VNEG_EN in register 0x0C. In this mode the internal shutdown timing of the VPOS and VNEG blocks is modified to allow for lower quiescent current in standby mode, therefore reducing the average current consumption during a sequence of on/off events.

7.3.2.4 Active Discharge

An optional active discharge is available for the VPOS and VNEG output rails. An internal switch resistance for this discharge function is implemented on each output rail. The VPOS active discharge function is enabled with register 0x0C bit[4] and the VNEG active discharge with register 0x0C bit[3].

7.3.2.5 LCM Bias Protection and Faults

The LCM Bias block of the LM3632A provides four protection mechanisms in order to prevent damage to the device. Note that none of these have any effect on backlight or flash operation.

7.3.3.1 Flash Boost Converter

The LM3632A incorporates a high-efficiency synchronous current-mode PWM boost converter that switches and boosts the output to maintain at least V_HR across the flash current source (FLED) over the 2.7-V to 5.5-V input voltage range. The flash boost has two switching frequency modes, 2-MHz and 4-MHz. These are set via the FL_FREQ Select bits, register 0x07 bits[7:6].

7.3.3.2 Start-Up (Enabling The Device)

The flash LED output (FLED) can be enabled in flash or torch mode with the Enable Register and the STROBE pin. The state of bit STROBE_EN, register 0x09 bit[4], determines if the FLED output is enabled by bit[1] of register 0x0A or the STROBE pin. Table 4 contains the details for flash operation control. While a positive edge is required at the STROBE pin in order to initiate a Torch or Flash event, the STROBE pin is level sensitive. That means that the event is terminated as soon as the STROBE pin transitions low.

On start-up, when V_OUT is less than V_IN the internal synchronous PFET turns on as a current source and delivers 200 mA (typical) to the output capacitor. During this time the current source (LED) is off. When the voltage across the output capacitor reaches 2.2 V (typical) the current source turns on. At turn-on the current source steps through each flash or torch level until the target LED current is reached. This gives the device a controlled turn-on and limits inrush current from the V_IN supply.

7.3.3.3 Pass Mode

The LM3632A flash boost starts up in pass mode and stays there until boost mode is needed to maintain regulation. If the voltage difference between V_{FL_OUT} and V_FLED falls below V_HR, the device switches to boost mode. In pass mode the boost converter does not switch, and the synchronous PFET turns fully on bringing V_{FL_OUT} up to V_IN − I_FLED × RPMOS. In pass mode the inductor current is not limited by the peak current limit.

7.3.3.4 Flash Mode

In flash mode, the LED current source (FLED) provides 15 target current levels from 100 mA to 1500 mA in 100 mA increments. The flash currents are adjusted via register 0x06 (see Table 12 for details). Once the flash sequence is activated the current source (FLED) ramps up to the programmed flash current by stepping through all current steps until the programmed current is reached. The headroom in the current source is regulated to provide 100 mA to 1.5 A to the output. Whether the device is enabled in flash mode through the Enable Register or through the STROBE pin, the Flash Enable bit in the Enable Register is cleared at the completion of the flash event and needs to be re-written in order to perform the next internal or external flash event.

7.3.3.5 Torch Mode

In torch mode, the LED current source (FLED) provides 15 target current levels from 25 mA to 375 mA in 25-mA increments. The torch currents are adjusted via register 0x06 (see Table 12 for details). Once the torch sequence is activated the current source (FLED) ramps up to the programmed Torch current by stepping through all current steps until the programmed current is reached. Torch mode is not affected by Flash Timeout or by a TX Interrupt event.

7.3.3.6 Power Amplifier Synchronization (TX)

The TX pin is a Power Amplifier Synchronization input. This is designed to reduce the flash FLED current and thus limit the battery current during high battery-current conditions such as PA transmit events. When the LM3632A is engaged in a flash event, and the TX pin is pulled high, the FLED current is forced into torch mode at the programmed torch current setting. If the TX pin is then pulled low before the flash pulse terminates, the FLED current returns to the previous flash current level. At the end of the flash time-out, whether the TX pin is high or low, the FLED current is turned off.

7.3.3.7 VIN Monitor

The LM3632A has the ability to adjust the flash current based upon the voltage level present at the VIN pin. The adjustable VINM threshold ranges from 2.6 V to 3.3 V in 100-mV steps. The Flags1 Register (0x0B) has the fault flag set when the input voltage crosses the VINM value. Additionally, the VINM threshold sets the input voltage boundary that forces the device to either transition into torch mode at the programmed torch current setting or turn off the FLED current for the remaining flash duration. This decision is made based on the status of bit VINM_MODE, register 0x09 bit[1]. In order to re-enable the LM3632A in torch or flash mode the VINM flag has to be cleared. If the VINM flag is tripped during flash current ramp-up, and VINM mode is set to torch, the FLED current is reduced not to the torch current setting but to the same percentage of the last flash current that was reached during fash current ramp-up. For example, if the flash current setting is 1 A, the torch current setting is 100 mA and the maximum flash current that was reached before the VINM threshold was crossed is 700 mA, the device will transition the flash current to 70 mA (70% of 100 mA).

7.3.3.8 Flash Fault Protections

7.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines should be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending whether it generates or receives the serial clock (SCL).

7.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 33. Data Validity

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software), and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

Figure 34. Acknowledge Signal

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 35. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

7.5.1.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

7.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

7.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LM3632A operates as a slave device with the 7-bit address. If an 8-bit address is used for programming, the 8th bit is '1' for read and '0' for write. The 7-bit address for the device is 0x11.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 36. I²C Device Address

Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master sends further data bytes the control register address is incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

Figure 37. Register Write Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in the Read Cycle waveform.

Figure 38. Register Read Format

Table 7. Revision Register Field Descriptions

Table 8. Backlight Configuration1 Register Field Descriptions

Table 9. Backlight Configuration2 Register Field Descriptions

Table 10. Backlight Brightness LSB Register Field Descriptions

Table 11. Backlight Brightness MSB Register Field Descriptions

Table 12. Flash/Torch Current Register Field Descriptions

Table 13. Flash Configuration Register Field Descriptions

Table 14. VIN Monitor Register Field Descriptions

Table 15. I/O Control Register Field Descriptions

Table 16. Enable Register Field Descriptions

Table 17. Flags1 Register Field Descriptions

Table 18. Display Bias Configuration Register Field Descriptions

Table 19. LCM Boost Bias Register Field Descriptions

Table 20. VPOS Bias Register Field Descriptions

Table 21. VNEG Bias Register Field Descriptions

Table 22. Flags2 Register Field Descriptions