SNVSA90 December   2014 LM5021-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operation Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Comparator and Slope Compensation
      2. 7.3.2 Current Limit and Current Sense
      3. 7.3.3 Oscillator, Shutdown and Sync Capability
      4. 7.3.4 Gate Driver and Max Duty Cycle Limit
      5. 7.3.5 Soft-Start
      6. 7.3.6 Hiccup Mode Overload Current Limiting
      7. 7.3.7 Skip Cycle Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN Below 20 V
      2. 7.4.2 Operation in Soft Start
      3. 7.4.3 Operation Under Normal Conditions
      4. 7.4.4 Operation in Skip Cycle
      5. 7.4.5 Operation at Overload
      6. 7.4.6 Operation in Hiccup Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Circuit
      2. 8.1.2 Relationship Between Input Capacitor CIN and VCC Capacitor CVCC
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Primary Bulk Capacitance
        2. 8.2.2.2 Transformer
        3. 8.2.2.3 Main Switch FET and Output Rectifier
        4. 8.2.2.4 Timing Resistor
        5. 8.2.2.5 Soft-Start Time
        6. 8.2.2.6 Current Sensing Network
          1. 8.2.2.6.1 Gate Drive Resistor
          2. 8.2.2.6.2 VCC Capacitor
          3. 8.2.2.6.3 Startup Circuit
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

In addition to following general power management IC layout guidelines (star grounding, minimal current loops, reasonable impedance levels, and so on) layout for the LM5021 should take into account the following:

  • If possible, a ground plane should be used to minimize the voltage drop on the ground circuit and the noise introduced by parasitic inductances in individual traces.
  • A decoupling capacitor is required for both the VIN pin and VCC pin and both should be returned to GND as close to the IC as possible. VIN is the more critical capacitor and should take first priority when connecting to GND as close as possible to the IC.
  • The timing setting components such as the RT pin resistor, SS pin capacitor should be directly connected to the ground plane or returned directly to the GND pin on their own traces.
  • The CS pin filter capacitor should be as close to the IC possible and grounded right at the IC ground pin. This ensures the best filtering effect and minimizes the chance of current sense pin malfunction.
  • Gate driver loop area should be minimized to reduce the EMI noise because of the high di/dt current in the loop.

10.2 Layout Example

LM5021-Q1 layouex1.gifFigure 26. Layout Example
LM5021-Q1 layoutrl_1_snvs359.pngFigure 27. Top Side View
LM5021-Q1 layoutrl_2_snvs359.pngFigure 28. Bottom Side View