The LM5067 negative hot swap controller provides intelligent control of the power supply connections during insertion and removal of circuit cards from a live system backplane or other “hot” power sources. The LM5067 provides in-rush current control to limit system voltage droop and transients. The current limit and power dissipation in the external series pass N-Channel MOSFET are programmable, ensuring operation within the Safe Operating Area (SOA). In addition, the LM5067 provides circuit protection by monitoring for over-current and over-voltage conditions. The POWER GOOD output indicates when the output voltage is close to the input voltage. The input under-voltage and over-voltage lockout levels and hysteresis are programmable, as well as the fault detection time. The LM5067-1 latches off after a fault detection, while the LM5067-2 automatically attempts restarts at a fixed duty cycle. The LM5067 is available in a 10-pin VSSOP package and a 14-pin SOIC package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5067 | VSSOP (10) | 3.00 mm x 3.00 mm |
SOIC (14) | 8.99 mm x 7.49 mm |
Changes from Revision C (March 2013) to Revision D (August 2020)
Changes from Revision B (September 2009) to Revision C (March 2013)
DEVICE NUMBER |
RETRY BEHAVIOR AFTER FAULT |
PACKAGE |
---|---|---|
LM5067-1 |
Latch-off |
VSSOP (10), SOIC (14) |
LM5067-2 |
Auto-retry |
VSSOP (10), SOIC (14) |
Name | Pin | I/O | Description | |
---|---|---|---|---|
VSSOP-10 | SOIC-14 | |||
VCC | 1 | 1 | I | Positive supply input: Connect to system ground through a resistor. Connect a bypass capacitor to VEE. The voltage from VCC to VEE is nominally 13 V set by an internal zener diode. |
UVLO/EN | 2 | 3 | I | Under-voltage lockout: An external resistor divider from the system input voltage sets the under-voltage turn-on threshold. The enable threshold at the pin is 2.5 V above VEE. An internal 22 µA current source provides hysteresis. This pin can be used for remote enable and disable. |
OVLO | 3 | 4 | I | Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. The disable threshold at the pin is 2.5 V above VEE. An internal 22 µA current source provides hysteresis. |
PWR | 4 | 5 | I | Power limit set: An external resistor at this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation in the external series pass MOSFET. |
VEE | 5 | 6 | I | Negative supply input: Connect to the system negative supply voltage (typically -48V). |
TIMER | 6 | 8 | I/O | Timing capacitor: An external capacitor at this pin sets the insertion time delay and the fault timeout period. The capacitor also sets the restart timing of the LM5067-2. |
SENSE | 7 | 9 | I | Current sense input: The voltage across the current sense resistor (RS) is measured from VEE to this pin. If the voltage across RS reaches 50 mV the load current is limited and the fault timer activates. |
GATE | 8 | 10 | O | Gate drive output: Connect to the external N-channel MOSFET’s gate. |
OUT | 9 | 12 | I | Output feedback: Connect to the external MOSFET’s drain. Internally used to determine the MOSFET VDS voltage for power limiting, and to control the PGD output pin. |
PGD | 10 | 14 | 0 | Power Good indicator: An open drain output capable of sustaining 80 V when off. When the external MOSFET VDS decreases below 1.23 V the PGD pin switches high. When the external MOSFET VDS increases above ≊2.5 V the PGD pin switches low. |