6.4 Thermal Information
THERMAL METRIC(1) |
LM5102 |
UNIT |
DGS |
DPR(2) |
10 PINS |
10 PINS |
RθJA |
Junction-to-ambient thermal resistance |
165.3 |
37.9 |
°C/W |
RθJC(top) |
Junction-to-case (top) thermal resistance |
58.9 |
38.1 |
RθJB |
Junction-to-board thermal resistance |
54.4 |
14.9 |
ψJT |
Junction-to-top characterization parameter |
6.2 |
0.4 |
ψJB |
Junction-to-board characterization parameter |
83.6 |
15.2 |
RθJC(bot) |
Junction-to-case (bottom) thermal resistance |
N/A |
4.4 |
(1) For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics application report (
SPRA953).
(2) Four-layer board with Cu finished thickness 1.5 oz, 1 oz, 1 oz, 1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50-mm × 50-mm ground and power planes embedded in PCB. See Application Note
AN-1187 Leadless Leadframe Package (LLP) (
SNOA401).
6.6 Switching Characteristics
MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ = +25°C, VDD = HB = 12 V, VSS = HS = 0 V, No Load on LO or HO(3).
SYMBOL |
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
tLPHL |
Lower Turn-Off Propagation Delay |
|
|
32 |
56 |
ns |
tHPHL |
Upper Turn-Off Propagation Delay |
|
|
32 |
56 |
tLPLH |
Lower Turn-On Propagation Delay |
RDT = 100k |
400 |
520 |
640 |
tHPLH |
Upper Turn-On Propagation Delay |
RDT = 100k |
450 |
570 |
690 |
tLPLH |
Lower Turn-On Propagation Delay |
RDT = 10k |
85 |
115 |
160 |
tHPLH |
Upper Turn-On Propagation Delay |
RDT = 10k |
85 |
115 |
160 |
ten, tsd |
Enable and Shutdown propagation delay |
|
|
36 |
|
DT1, DT2 |
Dead-time LO OFF to HO ON & HO OFF to LO ON |
RDT = 100k |
|
510 |
|
RDT = 10k |
|
86 |
|
MDT |
Dead-time matching |
RDT = 100k |
|
50 |
|
tR |
Either Output Rise Time |
CL = 1000pF |
|
15 |
|
tF |
Either Output Fall Time |
CL = 1000pF |
|
10 |
|
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur.
Recommended Operating Conditions are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the
Electrical Characteristics.
(2) Four-layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50-mm × 50-mm ground and power planes embedded in PCB. See
AN-1187 Leadless Leadframe Package (LLP),
SNOA401.
(3) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(4) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
(5) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V.