The LM5109B device is a cost-effective, high-voltage gate driver designed to drive both the high-side and the low-side N-channel MOSFETs in a synchronous buck or a half-bridge configuration. The floating
high-side driver is capable of working with rail voltages up to 90 V. The outputs are independently controlled with cost-effective TTL and
CMOS-compatible input thresholds. The robust level shift technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high-side gate driver. Undervoltage lockout is provided on both the low-side and the high-side power rails. The device is available in the 8-pin SOIC and thermally-enhanced 8-pin WSON packages.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5109B | SOIC (8) | 4.90 mm × 3.91 mm |
WSON (8) | 4.00 mm × 4.00 mm |
Changes from B Revision (March 2013) to C Revision
Changes from A Revision (March 2013) to B Revision
PIN | DESCRIPTION | |||
---|---|---|---|---|
NO.(2) | NAME | TYPE(1) | ||
1 | VDD | P | Positive gate drive supply – Locally decouple to VSS using low ESR and ESL capacitor located as close to IC as possible. | |
2 | HI | I | High-side control input – The HI input is compatible with TTL and CMOS input thresholds. Unused HI input must be tied to ground and not left open. | |
3 | LI | I | Low-side control input – The LI input is compatible with TTL and CMOS input thresholds. Unused LI input must be tied to ground and not left open. | |
4 | VSS | G | Ground – All signals are referenced to this ground. | |
5 | LO | O | Low-side gate driver output – Connect to the gate of the low-side N-MOS device. | |
6 | HS | P | High-side source connection – Connect to the negative terminal of the bootstrap capacitor and to the source of the high-side N-MOS device. | |
7 | HO | O | High-side gate driver output – Connect to the gate of the high-side N-MOS device. | |
8 | HB | P | High-side gate driver positive supply rail – Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor must be placed as close to IC as possible. |
MIN | MAX | UNIT | |
---|---|---|---|
VDD to VSS | –0.3 | 18 | V |
HB to HS | –0.3 | 18 | V |
LI or HI to VSS | –0.3 | VDD + 0.3 | V |
LO to VSS | –0.3 | VDD + 0.3 | V |
HO to VSS | VHS – 0.3 | VHB + 0.3 | V |
HS to VSS(2) | –5 | 90 | V |
HB to VSS | 108 | V | |
Junction temperature | –40 | 150 | °C |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | 8 | 14 | V | |
HS(1) | –1 | 90 | V | |
HB | VHS + 8 | VHS + 14 | V | |
HS slew rate | 50 | V/ns | ||
Junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | LM5109B | UNIT | ||
---|---|---|---|---|
D (SOIC) | NGT (WSON) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 117.6 | 42.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 64.9 | 34.0 | °C/W |
RθJB | Junction-to-board thermal resistance | 58.1 | 19.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 17.4 | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 57.6 | 19.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | – | 8.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CURRENTS | |||||||
IDD | VDD quiescent current | LI = HI = 0 V | TJ = 25°C | 0.3 | mA | ||
TJ = –40°C to 125°C | 0.6 | ||||||
IDDO | VDD operating current | f = 500 kHz | TJ = 25°C | 1.8 | mA | ||
TJ = –40°C to 125°C | 2.9 | ||||||
IHB | Total HB quiescent current | LI = HI = 0 V | TJ = 25°C | 0.06 | mA | ||
TJ = –40°C to 125°C | 0.2 | ||||||
IHBO | Total HB operating current | f = 500 kHz | TJ = 25°C | 1.4 | mA | ||
TJ = –40°C to 125°C | 2.8 | ||||||
IHBS | HB to VSS current, quiescent | VHS = VHB = 90 V | TJ = 25°C | 0.1 | µA | ||
TJ = –40°C to 125°C | 10 | ||||||
IHBSO | HB to VSS current, operating | f = 500 kHz | 0.5 | mA | |||
INPUT PINS LI AND HI | |||||||
VIL | Low level input voltage threshold | TJ = 25°C | 1.8 | V | |||
TJ = –40°C to 125°C | 0.8 | ||||||
VIH | High level input voltage threshold | TJ = 25°C | 1.8 | V | |||
TJ = –40°C to 125°C | 2.2 | ||||||
RI | Input pulldown resistance | TJ = 25°C | 200 | kΩ | |||
TJ = –40°C to 125°C | 100 | 500 | |||||
UNDERVOLTAGE PROTECTION | |||||||
VDDR | VDD rising threshold | VDDR = VDD – VSS | TJ = 25°C | 6.7 | V | ||
TJ = –40°C to 125°C | 6.0 | 7.4 | |||||
VDDH | VDD threshold hysteresis | 0.5 | V | ||||
VHBR | HB rising threshold | VHBR = VHB – VHS | TJ = 25°C | 6.6 | V | ||
TJ = –40°C to 125°C | 5.7 | 7.1 | |||||
VHBH | HB threshold hysteresis | 0.4 | V | ||||
LO GATE DRIVER | |||||||
VOLL | Low-level output voltage | ILO = 100 mA, VOHL = VLO – VSS | TJ = 25°C | 0.38 | V | ||
TJ = –40°C to 125°C | 0.65 | ||||||
VOHL | High-level output voltage | ILO = −100 mA, VOHL = VDD – VLO | TJ = 25°C | 0.72 | V | ||
TJ = –40°C to 125°C | 1.2 | ||||||
IOHL | Peak pullup current | VLO = 0 V | 1 | A | |||
IOLL | Peak pulldown current | VLO = 12 V | 1 | A | |||
HO GATE DRIVER | |||||||
VOLH | Low-level output voltage | IHO = 100 mA, VOLH = VHO – VHS | TJ = 25°C | 0.38 | V | ||
TJ = –40°C to 125°C | 0.65 | ||||||
VOHH | High-level output voltage | IHO = −100 mA, VOHH = VHB – VHO | TJ = 25°C | 0.72 | V | ||
TJ = –40°C to 125°C | 1.2 | ||||||
IOHH | Peak pullup current | VHO = 0 V | 1 | A | |||
IOLH | Peak pulldown current | VHO = 12 V | 1 | A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tLPHL | Lower turnoff propagation delay (LI falling to LO falling) |
TJ = 25°C | 30 | ns | ||
TJ = –40°C to 125°C | 56 | |||||
tHPHL | Upper turnoff propagation delay (HI falling to HO falling) |
TJ = 25°C | 30 | ns | ||
TJ = –40°C to 125°C | 56 | |||||
tLPLH | Lower turnon propagation delay (LI rising to LO rising) |
TJ = 25°C | 32 | ns | ||
TJ = –40°C to 125°C | 56 | |||||
tHPLH | Upper turnon propagation delay (HI rising to HO rising) |
TJ = 25°C | 32 | ns | ||
TJ = –40°C to 125°C | 56 | |||||
tMON | Delay matching: Lower turnon and upper turnoff | TJ = 25°C | 2 | ns | ||
TJ = –40°C to 125°C | 15 | |||||
tMOFF | Delay matching: Lower turnoff and upper turnon | TJ = 25°C | 2 | ns | ||
TJ = –40°C to 125°C | 15 | |||||
tRC, tFC | Either output rise and fall time | CL = 1000 pF | 15 | ns | ||
tPW | Minimum input pulse width that changes the output | 50 | ns |
VDD = VHB = 12 V | VSS = VHS = 0 V |
The LM5109B is a cost-effective, high-voltage gate driver designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL and CMOS-compatible input thresholds. The floating high-side driver is capable of working with HB voltage up to 108 V. An external high-voltage diode must be provided to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails.
Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each output until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition on the bootstrap capacitor (VHB–HS) will only disable the high-side output (HO).
CONDITION (VHB-HS > VHBR) | HI | LI | HO | LO |
---|---|---|---|---|
VDD-VSS < VDDR during device start-up | H | L | L | L |
VDD-VSS < VDDR during device start-up | L | H | L | L |
VDD-VSS < VDDR during device start-up | H | H | L | L |
VDD-VSS < VDDR during device start-up | L | L | L | L |
VDD-VSS < VDDR – VDDH after device start-up | H | L | L | L |
VDD-VSS < VDDR – VDDH after device start-up | L | H | L | L |
VDD-VSS < VDDR – VDDH after device start-up | H | H | L | L |
VDD-VSS < VDDR – VDDH after device start-up | L | L | L | L |
CONDITION (VDD > VDDR) | HI | LI | HO | LO |
---|---|---|---|---|
VHB-HS < VHBR during device start-up | H | L | L | L |
VHB-HS < VHBR during device start-up | L | H | L | H |
VHB-HS < VHBR during device start-up | H | H | L | H |
VHB-HS < VHBR during device start-up | L | L | L | L |
VHB-HS < VHBR – VHBH after device start-up | H | L | L | L |
VHB-HS < VHBR – VHBH after device start-up | L | H | L | H |
VHB-HS < VHBR – VHBH after device start-up | H | H | L | H |
VHB-HS < VHBR – VHBH after device start-up | L | L | L | L |
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and provides excellent delay matching with the low-side driver.
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high-peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS.
The device operates in normal mode and UVLO mode. See Start-Up and UVLO for more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided:
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
To operate power MOSFETs at high switching frequencies and to reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver.
The LM5109B is the high-voltage gate drivers designed to drive both the high-side and low-side N-channel MOSFETs in a half-bridge configuration, full-bridge configuration, or in a synchronous buck circuit. The floating high-side driver is capable of operating with supply voltages up to 90 V. This allows for N-channel MOSFETs control in half-bridge, full-bridge, push-pull, two-switch forward and active clamp topologies. The outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent flexibility to control ON and OFF-time of the output.
Table 4 lists the design parameters of the LM5109B.
PARAMETER | VALUE |
---|---|
Gate Driver | LM5109B |
MOSFET | CSD19534KCS |
VDD | 10 V |
QG | 17 nC |
fSW | 500 kHz |
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation. Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1.
where
Then, the total charge needed per switching cycle is estimated by Equation 2.
where
Therefore, the minimum CBoot must be:
In practice, the value of the CBoot capacitor must be greater than calculated to allow for situations where the power stage may skip pulse due to load transients. TI recommends having enough margins and place the bootstrap capacitor as close to the HB and HS pins as possible.
As a general rule the local VDD bypass capacitor must be 10 times greater than the value of CBoot, as shown in Equation 5.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric. The voltage rating must be twice that of the maximum VDD considering capacitance tolerances once the devices have a DC bias voltage across them and to ensure long-term reliability.
The bootstrap capacitor is charged by the VDD through the external bootstrap diode every cycle when low-side MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power dissipation in the bootstrap diode may be significant and the conduction loss also depends on its forward voltage drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver circuit.
For the selection of external bootstrap diodes, refer to AN-1317 Selection of External Bootstrap Diode for LM510X Devices, SNVA083. Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VHB-HS during each switching cycle, especially when HS pin have excessive negative transient voltage. RBOOT recommended value is between 2 Ω and 10 Ω depending on diode selection. A current limiting resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode, and the estimated peak current on the DBoot is shown in Equation 6.
where
The external gate driver resistor, RGATE, is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver.
Peak HO pullup current are calculated in Equation 7.
where
Similarly, Peak HO pulldown current is shown in Equation 8.
where
Peak LO pullup current is shown in Equation 9.
where
Peak LO pulldown current is shown in Equation 10.
where
For some scenarios, if the applications require fast turnoff, an anti-paralleled diode on RGate could be used to bypass the external gate drive resistor and speed up turnoff transition.
The total driver IC power dissipation can be estimated through the following components.
where
where
In this example, the estimated gate driver loss in LM5109B is shown in Equation 15.
For a given ambient temperature, the maximum allowable power loss of the IC can be defined as shown in Equation 16.
where
The thermal metrics for the driver package is summarized in the Thermal Information table of the data sheet. For detailed information regarding the thermal information table, please refer to the Texas Instruments application note entitled Semiconductor and IC Package Thermal Metrics (SPRA953).
Figure 15 and Figure 16 shows the rising and falling time as well as turnon and turnoff propagation delay testing waveform in room temperature, and waveform measurement data (see the bottom part of the waveform). Each channel (HI, LI, HO, and LO) is labeled and displayed on the left hand of the waveforms.
The testing condition: load capacitance is 1 nF, VDD = 12 V, fSW = 500 kHz.
HI and LI share one same input from function generator, therefore, besides the propagation delay and rising and falling time, the difference of the propagation delay between HO and LO gives the propagation delay matching data.
CL = 1 nF | VDD = 12 V | fSW = 500 kHz |
CL = 1 nF | VDD = 12 V | fSW = 500 kHz |
The recommended bias supply voltage range for LM5109B is from 8 V to 14 V. The lower end of this range is governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit blocks. The upper end of this range is driven by the 18-V absolute maximum voltage rating of the VDD. TI recommends keeping a 4-V margin to allow for transient voltage spikes.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in normal mode, if the VDD voltage drops, the device continues to operate in normal mode as long as the voltage drop does not exceed the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification, the device shuts down. Therefore, while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output must be smaller than the hysteresis specification of LM5109B to avoid triggering device-shutdown.
A local bypass capacitor must be placed between the VDD and GND pins. And this capacitor must be located as close to the device as possible. A low-ESR, ceramic surface mount capacitor is recommended. TI recommends using 2 capacitors across VDD and GND: a 100-nF, ceramic surface-mount capacitor for high-frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10-µF, for IC bias requirements. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore a 22-nF to 220-nF local decoupling capacitor is recommended between the HB and HS pins.
Optimum performance of high-side and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. The following points are emphasized: