SNVS477C February   2007  – January 2016 LM5109B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Level Shift
      3. 7.3.3 Output Stages
    4. 7.4 Device Functional Modes
    5. 7.5 HS Transient Voltages Below Ground
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Select External Bootstrap Diode and Its Series Resistor
        3. 8.2.2.3 Selecting External Gate Driver Resistor
        4. 8.2.2.4 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The LM5109B is a cost-effective, high-voltage gate driver designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL and CMOS-compatible input thresholds. The floating high-side driver is capable of working with HB voltage up to 108 V. An external high-voltage diode must be provided to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Start-Up and UVLO

Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each output until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition on the bootstrap capacitor (VHB–HS) will only disable the high-side output (HO).

Table 1. VDD UVLO Feature Logic Operation

CONDITION (VHB-HS > VHBR) HI LI HO LO
VDD-VSS < VDDR during device start-up H L L L
VDD-VSS < VDDR during device start-up L H L L
VDD-VSS < VDDR during device start-up H H L L
VDD-VSS < VDDR during device start-up L L L L
VDD-VSS < VDDR – VDDH after device start-up H L L L
VDD-VSS < VDDR – VDDH after device start-up L H L L
VDD-VSS < VDDR – VDDH after device start-up H H L L
VDD-VSS < VDDR – VDDH after device start-up L L L L

Table 2. VHB-HS UVLO Feature Logic Operation

CONDITION (VDD > VDDR) HI LI HO LO
VHB-HS < VHBR during device start-up H L L L
VHB-HS < VHBR during device start-up L H L H
VHB-HS < VHBR during device start-up H H L H
VHB-HS < VHBR during device start-up L L L L
VHB-HS < VHBR – VHBH after device start-up H L L L
VHB-HS < VHBR – VHBH after device start-up L H L H
VHB-HS < VHBR – VHBH after device start-up H H L H
VHB-HS < VHBR – VHBH after device start-up L L L L

7.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and provides excellent delay matching with the low-side driver.

7.3.3 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high-peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-Up and UVLO for more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.

Table 3. INPUT and OUTPUT Logic Table

HI LI HO(1) LO(2)
L L L L
L H L H
H L H L
H H H H
Floating Floating L L
(1) HO is measured with respect to the HS.
(2) LO is measured with respect to the VSS.

7.5 HS Transient Voltages Below Ground

The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided:

  1. HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible to be effective.
  2. HB to HS operating voltage must be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD must be ideally limited to 10 V to keep HB to HS below 15 V.
  3. Low-ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The capacitor must be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation.