SLVSFF1B December   2021  – December 2022 LM5123-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable/Disable (EN, VH Pin)
      2. 8.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 8.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 8.3.4  VOUT Range Selection (RANGE Pin)
      5. 8.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 8.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 8.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 8.3.8  Overvoltage Protection (VOUT Pin)
      9. 8.3.9  Power Good Indicator (PGOOD Pin)
      10. 8.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 8.3.11 External Clock Synchronization (SYNC Pin)
      12. 8.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 8.3.13 Programmable Soft Start (SS Pin)
      14. 8.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 8.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 8.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 8.3.17 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      18. 8.3.18 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      19. 8.3.19 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      20. 8.3.20 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Mode
        2. 8.4.2.2 Diode Emulation (DE) Mode
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGR|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-20200807-CA0I-FKCN-H5CH-DXTSMZVZ8HQC-low.gif 20-Pin QFN with Wettable Flanks RGR Package (Top View)
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
CSP 1 I Current sense amplifier input. The pin operates as the positive input pin.
CSN 2 I Current sense amplifier input. The pin operates as the negative input pin.
VOUT/SENSE 3 I Output voltage sensing pin. An internal feedback resistor voltage divider is connected from the pin to AGND. Connect a 0.1-μF local VOUT capacitor from the pin to ground.
High-side MOSFET drain voltage sensing pin. Connect the pin to the drain of the high-side MOSFET through a short, low inductance path.
PGOOD 4 O Power-good indicator with open-drain output stage. The pin is grounded when the output voltage is less than the undervoltage threshold. The pin can be left floating if not used.
HO 5 O High-side gate driver output. Connect directly to the gate of the high-side N-channel MOSFET through a short, low inductance path.
SW 6 P Switching node connection and the high-side MOSFET source voltage sensing pin. Connect directly to the source of the high-side N-channel MOSFET and the drain of the low-side N-channel MOSFET through a short, low inductance path. Connect to PGND for non-synchronous boost configuration.
HB 7 P High-side driver supply for bootstrap gate drive. Boot diode is internally connected from VCC to the pin. Connect a 0.1-μF capacitor between the pin and SW. Connect to VCC for non-synchronous boost configuration.
BIAS 8 P Supply voltage input to the VCC regulator. Connect a 1-μF local BIAS capacitor from the pin to ground.
VCC 9 P Output of the internal VCC regulator and supply voltage input of the internal MOSFET drivers. Connect a 4.7-μF capacitor between the pin and PGND.
PGND 10 G Power ground pin. Connect directly to the source of the low-side N-channel MOSFET and the power ground plane through a short, low inductance path.
LO 11 O Low-side gate driver output. Connect directly to the gate of the low-side N-channel MOSFET through a short, low inductance path.
MODE 12 I Device switching mode (FPWM, diode emulation, or skip) selection pin. The device is configured to skip mode if the pin is open or if a resistor that is greater than 500 kΩ is connected from the pin to AGND during initial power-on. The device is configured to FPWM mode by connecting the pin to VCC or if the pin voltage is greater than 2.0 V during power-on. The device is configured to diode emulation mode by connecting the pin to ground or the pin voltage is less than 0.4 V during initial power-on. The switching mode can be dynamically programmed between the FPWM and the DE mode during operation.
UVLO/EN 13 I Enable pin. The pin enables/disables the device. If the pin is less than 0.35 V, the device shuts down. The pin must be raised above 0.65 V to enable the device.
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting the pin to the supply voltage through a resistor voltage divider. The low-side UVLO resistor must be connected to AGND. Connect to BIAS if not used.
SYNC/DITHER/VH/CP 14 I/O Synchronization clock input. The internal oscillator can be synchronized to an external clock during operation. Connect to AGND if not used.
Clock dithering/spread spectrum modulation frequency programming pin. If a capacitor is connected between the pin and AGND, the clock dithering/spread spectrum function is activated. During the dithering operation, the capacitor is charged and discharged with an internal 20-μA current source/sink. As the voltage on the pin ramps up and down, the oscillator frequency is modulated between –6% and +5% of the nominal frequency set by the RT resistor. The clock dithering/spread spectrum can be deactivated during operation by pulling down the pin to ground.
VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when the EN pin is grounded, which helps to restart fast without reconfiguration.
Charge pump enable pin. If the pin is greater than 2.0 V, the internal charge pump maintains the HB pin voltage above its HB UVLO threshold for bypass operation, which allows the high-side switch to turn on 100% during bypass operation.
RT 15 I Switching frequency setting pin. If no external clock is applied to the SYNC pin, the switching frequency is programmed by a single resistor between the pin and AGND. Switching frequency is dynamically programmable during operation.
VREF/RANGE 16 I/O 1.0-V internal reference voltage output. Connect a 470-pF capacitor from the pin to AGND. The VOUT regulation target can be programmed by connecting a resistor voltage divider from the pin to TRK. The resistance from the pin to AGND must be always greater than 20 kΩ if used. Connect the low-side resistor of the divider to AGND.
VOUT range selection pin. Lower VOUT range (5 V to 20 V) is selected if the resistance from the pin to AGND is in the range of 75 kΩ and 100 kΩ during initial power-on. Upper VOUT range (15 V to 57 V) is selected if the resistance from the pin to AGND is in the range of 20 kΩ and 35 kΩ during initial power-on. Boost converter output voltage can be dynamically programmed within the pre-programmed range. The accuracy of the output voltage regulation is specified within the selected range.
SS 17 I/O Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. The device forces diode emulation during soft-start time.
TRK 18 I Output regulation target programming pin. The VOUT regulation target can be programmed by connecting the pin to VREF through a resistor voltage divider or by controlling the pin voltage directly from a D/A. The recommended operating range of the pin is from 0.25 V to 1.0 V.
AGND 19 G Analog ground pin. Connect to the analog ground plane through a wide and short path.
COMP 20 O Output of the internal transconductance error amplifier. Connect the loop compensation components between the pin and AGND.
EP — Exposed pad of the package. The EP must be soldered to a large analog ground plane to reduce thermal resistance.
(1) G = Ground, I = Input, O = Output, P = Power