SLVSES8A October   2020  – December 2020 LM5127-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable (EN, VCC_HOLD)
      2. 8.3.2  Dual Input VCC Regulator (BIAS, VCCX, VCC)
      3. 8.3.3  Dual Input VDD Switch (VDD, VDDX)
      4. 8.3.4  Device Configuration and Light Load Switching Mode Selection (CFG/MODE)
      5. 8.3.5  Fixed or Adjustable Output Regulation Target (VOUT, FB)
      6. 8.3.6  Overvoltage Protection (VOUT, FB)
      7. 8.3.7  Power Good Indicator (PGOOD)
      8. 8.3.8  Programmable Switching Frequency (RT)
      9. 8.3.9  External Clock Synchronization (SYNC)
      10. 8.3.10 Programmable Spread Spectrum (DITHER)
      11. 8.3.11 Programmable Soft Start (SS)
      12. 8.3.12 Fast Re-start using VCC_HOLD (VCC_HOLD)
      13. 8.3.13 Transconductance Error Amplifier and PWM (COMP)
      14. 8.3.14 Current Sensing and Slope Compensation (CSA, CSB)
      15. 8.3.15 Constant Peak Current Limit (CSA, CSB)
      16. 8.3.16 Maximum Duty Cycle and Minimum Controllable On-time Limits (Boost)
      17. 8.3.17 Bypass Mode (Boost)
      18. 8.3.18 Minimum Controllable On-time and Minimum Controllable Off-time Limits (Buck)
      19. 8.3.19 Low Dropout Mode for Extended Minimum Input Voltage (Buck)
      20. 8.3.20 Programmable Hiccup Mode Overload Protection (RES)
      21. 8.3.21 MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)
      22. 8.3.22 Battery Monitor (BMOUT, BMIN_FIX, BMIN_PRG)
      23. 8.3.23 Dual-phase Interleaved Configuration for High Current Supply (CFG)
      24. 8.3.24 Thermal Shutdown Protection
      25. 8.3.25 External VCCX Supply Reduces Power Dissipation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
          1. 8.4.1.5.1 Cutting Leakage Path in Deep Sleep Mode (DIS, SLEEP1, SENSE1)
        6. 8.4.1.6 VCC HOLD Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Operation
        2. 8.4.2.2 Diode Emulation (DE) Operation (Connect RSS at SS)
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode Operation
      3. 8.4.3 LM5127 Cheat Sheet
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Recommended Power Tree Architecture
        2. 9.2.2.2 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Programmable Hiccup Mode Overload Protection (RES)

The device includes programmable hiccup mode overload protection which is enabled when a capacitor (CRES) is connected to the RES pin in buck configuration. The hiccup mode overload protection is disabled in boost configuration or RES is connected to VDD during initial power-on.

In normal operation, CRES is discharged to ground and an internal fault counter counts the clocks when cycle-by-cycle current limiting occurs. When the fault counter detects 256 cycles of switching with current limit on any buck channel, an internal hiccup mode off-timer forces the applicable channel to stop switching and starts sourcing 20 μA of current (IRES) into CRES. During this hiccup mode overload protection, the off-time before the channel restart (TRES) is programmed by CRES. During TRES, the HO and the LO outputs are disabled and CSS is charged by IRES. When the RES pin voltage reaches the RES threshold (VRESTH) , CRES is discharged by an internal RES pull-down switch, and CSS begins to charge with 30us delay. The 256 cycle fault counter is reset if eight consecutive switching cycles occur without current limit.

GUID-20201006-CA0I-QVZP-VGPH-SNDDZRPBFB4Q-low.gif Figure 8-20 Hiccup Mode Overload Protection (Single Channel Fault)

The device provides an independent fault counter per channel, but the RES pin is shared by all channels. The device allows that one channel is in the hiccup mode off while the other channels operate normally. In the event that multiple channels are in a fault condition, the last fault counter pulls the RES pin low and starts the RES capacitor charging cycle. Then, the multiple channels which are in the fault condition restart together when the RES pin voltage reaches VRESTH. If CH2 and CH3 are configured as an interleaved dual-phase buck, the fault counters count the fault independently, but both CH2 and CH3 stop switching and restart together.

GUID-202EE599-D917-4269-A8A9-AFC653618824-low.gifFigure 8-21 Hiccup Mode Overload Protection (Multiple Channel Faults)

The hiccup mode protection is also programmed during the initial configuration time. If RES is connected to VDD during the initial configuration time, the internal fault counter is disabled and the device operates with non-hiccup mode cycle-by-cycle current limit. If RES is connected to AGND, the applicable channel that detects 256 cycles of current limiting stops switching and then never restarts until the applicable channel's EN pin is toggled.

GUID-68228057-995A-413A-9F04-943635162D7D-low.gifFigure 8-22 Hiccup Mode Configuration
Table 8-8 Overload Protection Configurations
RES SELECTIONSINGLE-PHASEDUAL-PHASE
CH1 : BOOSTCH1 : BUCKCH2 : BUCKCH3 : BUCKCH2//CH3 : BUCK
RES = VDDCycle-by-cycle current limitCycle-by-cycle current limit
RES =CRESHiccup mode current limit
RES = AGNDLatch-off mode current limit