SLVSES8A October   2020  – December 2020 LM5127-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable (EN, VCC_HOLD)
      2. 8.3.2  Dual Input VCC Regulator (BIAS, VCCX, VCC)
      3. 8.3.3  Dual Input VDD Switch (VDD, VDDX)
      4. 8.3.4  Device Configuration and Light Load Switching Mode Selection (CFG/MODE)
      5. 8.3.5  Fixed or Adjustable Output Regulation Target (VOUT, FB)
      6. 8.3.6  Overvoltage Protection (VOUT, FB)
      7. 8.3.7  Power Good Indicator (PGOOD)
      8. 8.3.8  Programmable Switching Frequency (RT)
      9. 8.3.9  External Clock Synchronization (SYNC)
      10. 8.3.10 Programmable Spread Spectrum (DITHER)
      11. 8.3.11 Programmable Soft Start (SS)
      12. 8.3.12 Fast Re-start using VCC_HOLD (VCC_HOLD)
      13. 8.3.13 Transconductance Error Amplifier and PWM (COMP)
      14. 8.3.14 Current Sensing and Slope Compensation (CSA, CSB)
      15. 8.3.15 Constant Peak Current Limit (CSA, CSB)
      16. 8.3.16 Maximum Duty Cycle and Minimum Controllable On-time Limits (Boost)
      17. 8.3.17 Bypass Mode (Boost)
      18. 8.3.18 Minimum Controllable On-time and Minimum Controllable Off-time Limits (Buck)
      19. 8.3.19 Low Dropout Mode for Extended Minimum Input Voltage (Buck)
      20. 8.3.20 Programmable Hiccup Mode Overload Protection (RES)
      21. 8.3.21 MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)
      22. 8.3.22 Battery Monitor (BMOUT, BMIN_FIX, BMIN_PRG)
      23. 8.3.23 Dual-phase Interleaved Configuration for High Current Supply (CFG)
      24. 8.3.24 Thermal Shutdown Protection
      25. 8.3.25 External VCCX Supply Reduces Power Dissipation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
          1. 8.4.1.5.1 Cutting Leakage Path in Deep Sleep Mode (DIS, SLEEP1, SENSE1)
        6. 8.4.1.6 VCC HOLD Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Operation
        2. 8.4.2.2 Diode Emulation (DE) Operation (Connect RSS at SS)
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode Operation
      3. 8.4.3 LM5127 Cheat Sheet
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Recommended Power Tree Architecture
        2. 9.2.2.2 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.21 MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)

The device provides N-channel logic MOSFET drivers which can source a peak current of 2.2 A and sink a peak current of 3.3 A. The drivers are powered by VCC or HB, and enabled when EN is greater than VEN and VCC is greater than VVCC-UVLO.

When the low-side driver turns on, the SW pin voltage is approximately 0 V and the CHB is charged from VCC through a boot diode. In boost configuration, the boot diode is internally connected from VCC to HB1. Connect external boot diodes in buck configuration. The recommended minimum value of CHB is 0.1-μF.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs are not enabled at the same time. When the device commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay. Similarly, the HO turnon is delayed until the LO-PGND voltage has discharged. HO is then enabled after a small delay. The adaptive dead-time circuit insures that both outputs are not enabled at the same time when QG@5V is less than 40 nC over the temperature.

If the minimum BIAS pin voltage is below VVCC-REG, extra care should be taken when selecting the MOSFETs. Especially during start-up at low BIAS input voltage, the gate plateau voltage of the MOSFET should be less than the BIAS pin voltage to completely enhance the MOSFET. If the driver output voltage is lower than the MOSFET gate plateau voltage during start-up, the converter may not start up properly and it can stick at the maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower threshold MOSFET or by turning on the channel when the BIAS pin voltage is sufficient.

GUID-20201214-CA0I-842N-4SQZ-7B8MD5B4ZTCB-low.gif Figure 8-23 Driver Structure (Internal boot diode is available only in boost)

The hiccup mode protection is triggered by the HB UVLO in boost configuration. If the HB-to-SW voltage is less than the HB UVLO threshold (VHB-UVLO), the LO turns on for 75 ns to replenish the boost capacitor. The device allows up to four consecutive replenish switchings. After four consecutive boot replenish switching, the channel skips the boot replenish switching for 12 cycles. If the channel fails to replenish the boost capacitor after the four sets of the four consecutive replenish switching, the channel stops switching and enters hiccup mode fault protection.

If required, the slew rate of the switching node voltage is adjusted by the resistor in series with the HB pin up to 5-Ω in buck configuration. If required, use a gate resistor in parallel with a pulldown PNP transistor. Care should be taken when adding a gate resistor as this can decrease the effective dead-time.

GUID-A4EE1ECE-34F4-4F0A-ADD2-599C677FFE88-low.gif Figure 8-24 Slew Rate Control (a) HB Resistor for Buck, (b) Gate Resistor with Pulldown PNP Transistor